Intel 386 User Manual
Intel386, Ex embedded microprocessor user’s manual
Table of contents
Document Outline
- Intel386 EX Embedded Microprocessor User’s Manual
- CONTENTS
- CHAPTER 1 GUIDE TO THIS MANUAL
- CHAPTER 2 ARCHITECTURAL OVERVIEW
- CHAPTER 3 CORE OVERVIEW
- CHAPTER 4 SYSTEM REGISTER ORGANIZATION
- CHAPTER 5 DEVICE CONFIGURATION
- 5.1 Introduction
- 5.2 Peripheral Configuration
- 5.2.1 DMA Controller, Bus Arbiter, and Refresh Uni...
- 5.2.1.1 Using The DMA Unit with External Devices
- 5.2.1.2 DMA Service to an SIO or SSIO Peripheral
- 5.2.1.3 Using The Timer To Initiate DMA Transfers
- 5.2.1.4 Limitations Due To Pin Signal Multiplexing...
- 5.2.2 Interrupt Control Unit Configuration
- 5.2.3 Timer/counter Unit Configuration
- 5.2.4 Asynchronous Serial I/O Configuration
- 5.2.5 Synchronous Serial I/O Configuration
- 5.2.6 Chip-select Unit and Clock and Power Managem...
- 5.2.7 Core Configuration
- 5.3 Pin Configuration
- 5.4 Device Configuration Procedure
- 5.5 Configuration Example
- 5.2.1 DMA Controller, Bus Arbiter, and Refresh Uni...
- CHAPTER 6 BUS INTERFACE UNIT
- CHAPTER 7 SYSTEM MANAGEMENT MODE
- 7.1 System Management Mode Overview
- 7.2 SMM Hardware Interface
- 7.3 System Management Mode Programming and Configu...
- 7.4 The Intel386 EX Processor Identifier Registers...
- 7.5 Programming Considerations
- CHAPTER 8 CLOCK AND POWER MANAGEMENT UNIT
- CHAPTER 9 INTERRUPT CONTROL UNIT
- 9.1 Overview
- 9.2 ICU operation
- 9.3 Register Definitions
- 9.3.1 Port 3 Configuration Register (P3CFG)
- 9.3.2 Interrupt Configuration Register (INTCFG)
- 9.3.3 Initialization Command Word 1 (ICW1)
- 9.3.4 Initialization Command Word 2 (ICW2)
- 9.3.5 Initialization Command Word 3 (ICW3)
- 9.3.6 Initialization Command Word 4 (ICW4)
- 9.3.7 Operation Command Word 1 (OCW1)
- 9.3.8 Operation Command Word 2 (OCW2)
- 9.3.9 Operation Command Word 3 (OCW3)
- 9.3.10 Interrupt Request Register (IRR)
- 9.3.11 In-Service Register (ISR)
- 9.3.12 Poll Status Byte (POLL)
- 9.4 Design Considerations
- 9.5 Programming Considerations
- CHAPTER 10 TIMER/COUNTER UNIT
- CHAPTER 11 ASYNCHRONOUS SERIAL I/O UNIT
- 11.1 Overview
- 11.2 SIO Operation
- 11.3 Register Definitions
- 11.3.1 Pin and Port Configuration Registers (PINCF...
- 11.3.2 SIO and SSIO Configuration Register (SIOCFG...
- 11.3.3 Divisor Latch Registers (DLLn and DLHn)
- 11.3.4 Transmit Buffer Register (TBRn)
- 11.3.5 Receive Buffer Register (RBRn)
- 11.3.6 Serial Line Control Register (LCRn)
- 11.3.7 Serial Line Status Register (LSRn)
- 11.3.8 Interrupt Enable Register (IERn)
- 11.3.9 Interrupt ID Register (IIRn)
- 11.3.10 Modem Control Register (MCRn)
- 11.3.11 Modem Status Register (MSRn)
- 11.3.12 Scratch Pad Register (SCRn)
- 11.4 Programming Considerations
- CHAPTER 12 DMA CONTROLLER
- 12.1 Overview
- 12.2 DMA Operation
- 12.2.1 DMA Transfers
- 12.2.2 Bus Cycle Options for Data Transfers
- 12.2.3 Starting DMA Transfers
- 12.2.4 Bus Control Arbitration
- 12.2.5 Ending DMA Transfers
- 12.2.6 Buffer-transfer Modes
- 12.3 Register Definitions
- 12.3.1 Pin Configuration Register (PINCFG)
- 12.3.2 DMA Configuration Register (DMACFG)
- 12.3.3 Channel Registers
- 12.3.4 Overflow Enable Register (DMAOVFE)
- 12.3.5 Command 1 Register (DMACMD1)
- 12.3.6 Status Register (DMASTS)
- 12.3.7 Command 2 Register (DMACMD2)
- 12.3.8 Mode 1 Register (DMAMOD1)
- 12.3.9 Mode 2 Register (DMAMOD2)
- 12.3.10 Software Request Register (DMASRR)
- 12.3.11 Channel Mask and Group Mask Registers (DMA...
- 12.3.12 Bus Size Register (DMABSR)
- 12.3.13 Chaining Register (DMACHR)
- 12.3.14 Interrupt Enable Register (DMAIEN)
- 12.3.15 Interrupt Status Register (DMAIS)
- 12.3.16 Software Commands
- 12.4 Design Considerations
- 12.5 Programming Considerations
- CHAPTER 13 SYNCHRONOUS SERIAL I/O UNIT
- 13.1 Overview
- 13.2 SSIO Operation
- 13.3 Register Definitions
- 13.3.1 Pin Configuration Register (PINCFG)
- 13.3.2 SIO and SSIO Configuration Register (SIOCFG...
- 13.3.3 Prescale Clock Register (CLKPRS)
- 13.3.4 SSIO Baud-rate Control Register (SSIOBAUD)
- 13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR...
- 13.3.6 SSIO Control 1 Register (SSIOCON1)
- 13.3.7 SSIO Control 2 Register (SSIOCON2)
- 13.3.8 SSIO Transmit Holding Buffer (SSIOTBUF)
- 13.3.9 SSIO Receive Holding Buffer (SSIORBUF)
- 13.4 Design Considerations
- 13.5 Programming Considerations
- CHAPTER 14 CHIP-SELECT UNIT
- CHAPTER 15 REFRESH CONTROL UNIT
- CHAPTER 16 INPUT/OUTPUT PORTS
- CHAPTER 17 WATCHDOG TIMER UNIT
- CHAPTER 18 JTAG TEST-LOGIC UNIT
- APPENDIX A SIGNAL DESCRIPTIONS
- APPENDIX B COMPATIBILITY WITH THE PC/AT* ARCHITECT...
- APPENDIX C EXAMPLE CODE HEADER FILES
- APPENDIX D SYSTEM REGISTER QUICK REFERENCE
- D.1 Peripheral Register Addresses
- D.2 CLKPRS
- D.3 CSnADH (UCSADH)
- D.4 CSnADL (UCSADL)
- D.5 CSnMSKH (UCSMSKH)
- D.6 CSnMSKL (UCSMSKL)
- D.7 DLLn and DLHn
- D.8 DMABSR
- D.9 DMACFG
- D.10 DMACHR
- D.11 DMACMD1
- D.12 DMACMD2
- D.13 DMAGRPMSK
- D.14 DMAIEN
- D.15 DMAIS
- D.16 DMAMOD1
- D.17 DMAMOD2
- D.18 DMAMSK
- D.19 DMAnBYCn, DMAnREQn and DMAnTARn
- D.20 DMAOVFE
- D.21 DMASRR
- D.22 DMASTS
- D.23 ICW1 (master and slave)
- D.24 ICW2 (master and slave)
- D.25 ICW3 (master)
- D.26 ICW3 (slave)
- D.27 ICW4 (master and slave)
- D.28 IDCODE
- D.29 IERn
- D.30 IIRn
- D.31 INTCFG
- D.32 IR
- D.33 LCRn
- D.34 LSRn
- D.35 MCRn
- D.36 MSRn
- D.37 OCW1 (master and slave)
- D.38 OCW2 (master and slave)
- D.39 OCW3 (master and slave)
- D.40 P1CFG
- D.41 P2CFG
- D.42 P3CFG
- D.43 PINCFG
- D.44 PNDIR
- D.45 PnLTC
- D.46 PnPIN
- D.47 POLL (master and slave)
- D.48 PORT92
- D.49 PWRCON
- D.50 RBRn
- D.51 REMAPCFG
- D.52 RFSADD
- D.53 RFSBAD
- D.54 RFSCIR
- D.55 RFSCON
- D.56 SCRn
- D.57 SIOCFG
- D.58 SSIOBAUD
- D.59 SSIOCON1
- D.60 SSIOCON2
- D.61 SSIOCTR
- D.62 SSIORBUF
- D.63 SSIOTBUF
- D.64 TBRn
- D.65 TMRCFG
- D.66 TMRCON
- D.67 TMRn
- D.68 UCSADH
- D.69 UCSADL
- D.70 UCSMSKH
- D.71 UCSMSKL
- D.72 WDTCNTH and WDTCNTL
- D.73 WDTRLDH and WDTRLDL
- D.74 WDTSTATUS
- APPENDIX E INSTRUCTION SET SUMMARY
- E.1 Instruction Encoding and Clock Count Summary
- E.2 Instruction Encoding
- E.2.1 32-bit Extensions of the Instruction Set
- E.2.2 Encoding of Instruction Fields
- E.2.2.1 Encoding of Operand Length (w) Field
- E.2.2.2 Encoding of the General Register (reg) Fie...
- E.2.2.3 Encoding of the Segment Register (sreg) Fi...
- E.2.2.4 Encoding of Address Mode
- E.2.2.5 Encoding of Operation Direction (d) Field
- E.2.2.6 Encoding of Sign-Extend (s) Field
- E.2.2.7 Encoding of Conditional Test (tttn) Field
- E.2.2.8 Encoding of Control or Debug or Test Regis...
- GLOSSARY
- INDEX
- Figures
- Figure 21. Intel386™ EX Embedded Processor Block ...
- Figure 31. Instruction Pipelining
- Figure 32. The Intel386™ CX Processor Internal Bl...
- Figure 41. PC/AT I/O Address Space (10-bit Decode...
- Figure 42. Expanded I/O Address Space (16-bit Dec...
- Figure 43. Address Configuration Register (REMAPC...
- Figure 44. Setting the ESE Bit Code Example
- Figure 45. DOS-Compatible Mode
- Figure 46. Example of Nonintrusive DOS-Compatible...
- Figure 47. Enhanced DOS Mode
- Figure 48. NonDOS Mode
- Figure 51. Peripheral and Pin Connections
- Figure 52. Configuration of DMA, Bus Arbiter, and...
- Figure 53. DMA Configuration Register (DMACFG)
- Figure 54. Interrupt Control Unit Configuration
- Figure 55. Interrupt Configuration Register (INTC...
- Figure 56. Timer/Counter Unit Configuration
- Figure 57. Timer Configuration Register (TMRCFG)
- Figure 58. Serial I/O Unit 0 Configuration
- Figure 59. Serial I/O Unit 1 Configuration
- Figure 510. SIO and SSIO Configuration Register (...
- Figure 511. SSIO Unit Configuration
- Figure 512. Configuration of Chip-select Unit and...
- Figure 513. Core Configuration
- Figure 514. Port 92 Configuration Register (PORT9...
- Figure 515. Pin Configuration Register (PINCFG)
- Figure 516. Port 1 Configuration Register (P1CFG)...
- Figure 517. Port 2 Configuration Register (P2CFG)...
- Figure 518. Port 3 Configuration Register (P3CFG)...
- Figure 61. Basic External Bus Cycles
- Figure 62. Simplified Bus State Diagram (Does Not...
- Figure 63. Ready Logic
- Figure 64. Basic Internal and External Bus Cycles...
- Figure 65. Nonpipelined Address Read Cycles
- Figure 66. Nonpipelined Address Write Cycles
- Figure 67. Complete Bus States (Including Pipelin...
- Figure 68. Pipelined Address Cycles
- Figure 69. Interrupt Acknowledge Cycles
- Figure 610. Halt Cycle
- Figure 611. Basic Refresh Cycle
- Figure 612. Refresh Cycle During HOLD/HLDA
- Figure 613. 16-bit Cycles to 8-bit Devices (Using...
- Figure 614. LOCK# Signal During Address Pipelinin...
- Figure 615. Intel386 EX Processor to Intel387 SX ...
- Figure 616. Intel386 EX Processor to SRAM/FLASH I...
- Figure 617. Intel386 EX Processor to PSRAM Interf...
- Figure 618. Intel386 EX Processor to Paged DRAM I...
- Figure 619. Intel386 EX Processor and Non-Paged D...
- Figure 71. Standard SMI#
- Figure 72. SMIACT# Latency
- Figure 73. SMI# During HALT
- Figure 74. SMI# During I/O Instruction
- Figure 75. SMI# Timing
- Figure 76. Interrupted SMI# Service
- Figure 77. HALT During SMM Handler
- Figure 81. Clock and Power Management Unit Connec...
- Figure 82. Clock Synchronization
- Figure 83. SMM Interaction with Idle and Powerdow...
- Figure 84. Clock Prescale Register (CLKPRS)
- Figure 85. Power Control Register (PWRCON)
- Figure 86. Timing Diagram, Entering and Leaving I...
- Figure 87. Timing Diagram, Entering and Leaving P...
- Figure 88. Reset Synchronization Circuit
- Figure 91. Interrupt Control Unit Configuration
- Figure 92. Methods for Changing the Default Inter...
- Figure 93. Interrupt Process – Master Request fro...
- Figure 94. Interrupt Process – Slave Request
- Figure 95. Interrupt Process – Master Request fro...
- Figure 96. Port 3 Configuration Register (P3CFG)
- Figure 97. Interrupt Configuration Register (INTC...
- Figure 98. Initialization Command Word 1 Register...
- Figure 99. Initialization Command Word 2 Register...
- Figure 910. Initialization Command Word 3 Registe...
- Figure 911. Initialization Command Word 3 Registe...
- Figure 912. Initialization Command Word 4 Registe...
- Figure 913. Operation Command Word 1 (OCW1)
- Figure 914. Operation Command Word 2 (OCW2)
- Figure 915. Operation Command Word 3 (OCW3)
- Figure 916. Poll Status Byte (POLL)
- Figure 917. Interrupt Acknowledge Cycle
- Figure 918. Spurious Interrupts
- Figure 919. Cascading External 82C59A Interrupt C...
- Figure 101. Timer/Counter Unit Signal Connections...
- Figure 102. Mode 0 – Basic Operation
- Figure 103. Mode 0 – Disabling the Count
- Figure 104. Mode 0 – Writing a New Count
- Figure 105. Mode 1 – Basic Operation
- Figure 106. Mode 1 – Retriggering the One-shot
- Figure 107. Mode 1 – Writing a New Count
- Figure 108. Mode 2 – Basic Operation
- Figure 109. Mode 2 – Disabling the Count
- Figure 1010. Mode 2 – Writing a New Count
- Figure 1011. Mode 3 – Basic Operation (Even Count...
- Figure 1012. Mode 3 – Basic Operation (Odd Count)...
- Figure 1013. Mode 3 – Disabling the Count
- Figure 1014. Mode 3 – Writing a New Count (With a...
- Figure 1015. Mode 3 – Writing a New Count (Withou...
- Figure 1016. Mode 4 – Basic Operation
- Figure 1017. Mode 4 – Disabling the Count
- Figure 1018. Mode 4 – Writing a New Count
- Figure 1019. Mode 5 – Basic Operation
- Figure 1020. Mode 5 – Retriggering the Strobe
- Figure 1021. Mode 5 – Writing a New Count Value
- Figure 1022. Timer Configuration Register (TMRCFG...
- Figure 1023. Port 3 Configuration Register (P3CFG...
- Figure 1024. Pin Configuration Register (PINCFG)
- Figure 1025. Timer Control Register (TMRCON – Con...
- Figure 1026. Timer n Register (TMRn – Write Forma...
- Figure 1027. Timer Control Register (TMRCON – Cou...
- Figure 1028. Timer n Register (TMRn – Read Format...
- Figure 1029. Timer Control Register (TMRCON – Rea...
- Figure 1030. Timer n Register (TMRn – Status Form...
- Figure 111. Serial I/O Unit 1 Configuration
- Figure 112. SIOn Baud-rate Generator Clock Source...
- Figure 113. SIOn Transmitter
- Figure 114. SIOn Data Transmission Process Flow
- Figure 115. SIOn Receiver
- Figure 116. SIOn Data Reception Process Flow
- Figure 117. Pin Configuration Register (PINCFG)
- Figure 118. Port 1 Configuration Register (P1CFG)...
- Figure 119. Port 2 Configuration Register (P2CFG)...
- Figure 1110. Port 3 Configuration Register (P3CFG...
- Figure 1111. SIO and SSIO Configuration Register ...
- Figure 1112. Divisor Latch Registers (DLLn and DL...
- Figure 1113. Transmit Buffer Register (TBRn)
- Figure 1114. Receive Buffer Register (RBRn)
- Figure 1115. Serial Line Control Register (LCRn)
- Figure 1116. Serial Line Status Register (LSRn)
- Figure 1117. Interrupt Enable Register (IERn)
- Figure 1118. Interrupt ID Register (IIRn)
- Figure 1119. Modem Control Signals – Diagnostic M...
- Figure 1120. Modem Control Signals – Internal Con...
- Figure 1121. Modem Control Register (MCRn)
- Figure 1122. Modem Status Register (MSRn)
- Figure 1123. Scratch Pad Register (SCRn)
- Figure 121. DMA Unit Block Diagram
- Figure 122. DMA Temporary Buffer Operation for a ...
- Figure 123. DMA Temporary Buffer Operation for A ...
- Figure 124. Start of a Two-cycle DMA Transfer Ini...
- Figure 125. Changing the Priority of the DMA Chan...
- Figure 126. Buffer Transfer Ended by an Expired B...
- Figure 127. Buffer Transfer Ended by the EOP# Inp...
- Figure 128. Single Data-transfer Mode with Single...
- Figure 129. Single Data-transfer Mode with Autoin...
- Figure 1210. Single Data-transfer Mode with Chain...
- Figure 1211. Block Data-transfer Mode with Single...
- Figure 1212. Block Data-transfer Mode with Autoin...
- Figure 1213. Buffer Transfer Suspended by the Dea...
- Figure 1214. Demand Data-transfer Mode with Singl...
- Figure 1215. Demand Data-transfer Mode with Autoi...
- Figure 1216. Demand Data-transfer Mode with Chain...
- Figure 1217. Cascade Mode
- Figure 1218. Pin Configuration Register (PINCFG)
- Figure 1219. DMA Configuration Register (DMACFG)
- Figure 1220. DMA Channel Address and Byte Count R...
- Figure 1221. DMA Overflow Enable Register (DMAOVF...
- Figure 1222. DMA Command 1 Register (DMACMD1)
- Figure 1223. DMA Status Register (DMASTS)
- Figure 1224. DMA Command 2 Register (DMACMD2)
- Figure 1225. DMA Mode 1 Register (DMAMOD1)
- Figure 1226. DMA Mode 2 Register (DMAMOD2)
- Figure 1227. DMA Software Request Register (DMASR...
- Figure 1228. DMA Software Request Register (DMASR...
- Figure 1229. DMA Channel Mask Register (DMAMSK)
- Figure 1230. DMA Group Channel Mask Register (DMA...
- Figure 1231. DMA Bus Size Register (DMABSR)
- Figure 1232. DMA Chaining Register (DMACHR)
- Figure 1233. DMA Interrupt Enable Register (DMAIE...
- Figure 1234. DMA Interrupt Status Register (DMAIS...
- Figure 131. Transmitter and Receiver in Master Mo...
- Figure 132. Transmitter in Master Mode, Receiver ...
- Figure 133. Transmitter in Slave Mode, Receiver i...
- Figure 134. Transmitter and Receiver in Slave Mod...
- Figure 135. Clock Sources for the Baud-rate Gener...
- Figure 136. SSIO Transmitter with Autotransmit Mo...
- Figure 137. SSIO Transmitter with Autotransmit Mo...
- Figure 138. Transmit Data by Polling
- Figure 139. Interrupt Service Routine for Transmi...
- Figure 1310. Transmitter Master Mode, Single Word...
- Figure 1311. Transmitter Master Mode, Single Word...
- Figure 1312. Receive Data by Polling
- Figure 1313. Interrupt Service Routine for Receiv...
- Figure 1314. Receiver Master Mode, Single Word Tr...
- Figure 1315. Pin Configuration Register (PINCFG)
- Figure 1316. SIO and SSIO Configuration Register ...
- Figure 1317. Clock Prescale Register (CLKPRS)
- Figure 1318. SSIO Baud-rate Control Register (SSI...
- Figure 1319. SSIO Baud-rate Count Down Register (...
- Figure 1320. SSIO Control 1 Register (SSIOCON1)
- Figure 1321. SSIO Control 2 Register (SSIOCON2)
- Figure 1322. SSIO Transmit Holding Buffer (SSIOTB...
- Figure 1323. SSIO Receive Holding Buffer (SSIORBU...
- Figure 141. Channel Address Comparison Logic
- Figure 142. Determining a Channel’s Address Block...
- Figure 143. Bus Cycle Length Adjustments for Over...
- Figure 144. Pin Configuration Register (PINCFG)
- Figure 145. Port 2 Configuration Register (P2CFG)...
- Figure 146. Chip-select High Address Register (CS...
- Figure 147. Chip-select Low Address Register (CSn...
- Figure 148. Chip-select High Mask Registers (CSnM...
- Figure 149. Chip-select Low Mask Registers (CSnMS...
- Figure 151. Refresh Control Unit Connections
- Figure 152. Refresh Clock Interval Register (RFSC...
- Figure 153. Refresh Control Register (RFSCON)
- Figure 154. Refresh Base Address Register (RFSBAD...
- Figure 155. Refresh Address Register (RFSADD)
- Figure 156. Connections to Ensure Refresh of All ...
- Figure 157. RAS# Only Refresh Logic: Paged Mode
- Figure 158. RAS# Only Refresh Logic: Non-Paged Mo...
- Figure 161. I/O Port Block Diagram
- Figure 162. Logic Diagram of a Bi-directional Por...
- Figure 163. Port n Configuration Register (PnCFG)...
- Figure 164. Port Direction Register (PnDIR)
- Figure 165. Port Data Latch Register (PnLTC)
- Figure 166. Port Pin State Register (PnPIN)
- Figure 171. Watchdog Timer Unit Connections
- Figure 172. WDT Counter Value Registers (WDTCNTH ...
- Figure 173. WDT Status Register (WDTSTATUS)
- Figure 174. WDT Reload Value Registers (WDTRLDH a...
- Figure 175. Power Control Register (PWRCON)
- Figure 181. Test Logic Unit Connections
- Figure 182. TAP Controller (Finite-State Machine)...
- Figure 183. Instruction Register (IR)
- Figure 184. Identification Code Register (IDCODE)...
- Figure 185. Internal and External Timing for Load...
- Figure 186. Internal and External Timing for Load...
- Figure B1. Derivation of AEN Signal in a Typical ...
- Figure B2. Derivation of AEN Signal for Intel386™...
- Figure E1. General Instruction Format
- Tables
- Table 21. PC-compatible Peripherals
- Table 22. Embedded Application-specific Periphera...
- Table 41. Peripheral Register I/O Address Map in ...
- Table 42. Peripheral Register Addresses (Sheet 6 ...
- Table 51. Master’s IR3 Connections
- Table 52. Master’s IR4 Connections
- Table 53. Signal Pairs on Pins without a Multiple...
- Table 54. Example Pin Configuration Registers
- Table 55. Example DMACFG Configuration Register
- Table 56. Example TMRCFG Configuration Register
- Table 57. Example INTCFG Configuration Register
- Table 58. Example SIOCFG Configuration Register
- Table 59. Pin Configuration Register Design Woksh...
- Table 510. DMACFG Register Design Worksheet
- Table 511. TMRCFG Register Design Worksheet
- Table 512. INTCFG Register Design Worksheet
- Table 513. SIOCFG Register Design Worksheet
- Table 61. Bus Interface Unit Signals (Sheet 2 of ...
- Table 62. Bus Status Definitions
- Table 63. Sequence of Nonaligned Bus Transfers
- Table 71. CR0 Bits Cleared Upon Entering SMM
- Table 72. SMM Processor State Initialization Valu...
- Table 73. Relative Priority of Exceptions and Int...
- Table 81. Clock and Power Management Registers
- Table 82. Clock and Power Management Signals
- Table 91. 82C59A Master and Slave Interrupt Sourc...
- Table 92. ICU Registers(Sheet 2 of 2)
- Table 101. TCU Signals
- Table 102. TCU Associated Registers
- Table 103. Operations Caused by GATEn
- Table 104. GATEn Connection Options
- Table 105. Minimum and Maximum Initial Counts
- Table 106. Results of Multiple Read-back Commands...
- Table 111. SIO Signals
- Table 112. Maximum and Minimum Output Bit Rates
- Table 113. Divisor Values for Common Bit Rates
- Table 114. Status Signal Priorities and Sources
- Table 115. SIO Registers(Sheet 2 of 2)
- Table 116. Access to Multiplexed Registers
- Table 121. DMA Signals
- Table 122. Operations Performed During Transfer
- Table 123. DMA Registers (Sheet 3 of 3)
- Table 124. DMA Software Commands
- Table 131. SSIO Signals
- Table 132. Maximum and Minimum Baud-rate Output F...
- Table 133. SSIO Registers
- Table 141. CSU Signals
- Table 142. CSU Registers
- Table 151. RCU Signals
- Table 152. RCU Registers
- Table 161. Pin Multiplexing
- Table 162. I/O Port Registers
- Table 163. Control Register Values for I/O Port P...
- Table 171. WDT Signals
- Table 172. WDT Registers
- Table 181. Test Access Port Dedicated Pins
- Table 182. TAP Controller State Descriptions (She...
- Table 183. Example TAP Controller State Selection...
- Table 184. Test-logic Unit Instructions
- Table 185. Boundary-scan Register Bit Assignments...
- Table A1. Signal Description Abbreviations
- Table A2. Description of Signals Available at the...
- Table A3. Pin State Abbreviations
- Table A4. Pin States After Reset and During Idle,...
- Table D1. Peripheral Register Addresses (Sheet 6 ...
- Table E1. Instruction Set Summary(Sheet 19 of 1...
- Table E2. Fields Within Instructions
- Table E3. Encoding of Operand Length (w) Field
- Table E4. Encoding of reg Field When w Field is n...
- Table E5. Encoding of reg Field When w Field is P...
- Table E6. Encoding of the Segment Register (sreg)...
- Table E7. Encoding of 16-bit Address Mode with “m...
- Table E8. Encoding of 32-bit Address Mode with “m...
- Table E9. Encoding of 32-bit Address Mode (“mod r...
- Table E10. Encoding of Operation Direction (d) Fi...
- Table E11. Encoding of Sign-Extend (s) Field
- Table E12. Encoding of Conditional Test (tttn) Fi...
- Table E13. When Interpreted as Control Register F...
- Table E14. When Interpreted as Debug Register Fie...
- Table E15. When Interpreted as Test Register Fiel...