Intel 386 - Manual (Page 237)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
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/* ICU IRQ Mask Values*/
#define IR0 0x1
#define IR1 0x2
#define IR2 0x4
#define IR3 0x8
#define IR4 0x10
#define IR5 0x20
#define IR6 0x40
#define IR7 0x80
Enable8259Interrupts(IR2, IR0 | IR7); //Enable MasterIR2 for cascading
//Enable INT4 and WDTOUT on Slave
Real/Protected Mode
No changes required.
*****************************************************************************/
void Enable8259Interrupt(BYTE MstrMask, BYTE SlaveMask)
{
BYTE Mask;
if(MstrMask != 0)
{
Mask = _GetEXRegByte(OCW1M);
_SetEXRegByte(OCW1M, Mask & (~MstrMask));
}
if(SlaveMask != 0)
{
Mask = _GetEXRegByte(OCW1S);
_SetEXRegByte(OCW1S, Mask & (~SlaveMask));
}
}/* Enable8259Interrupt */
/****************************************************************************
SetIRQVector:
Description:
Loads the interrupt vector table with the address of the interrupt
routine. The vector table entry number is determined by the vector
number.
Parameters:
InterProc Address of interrupt function, will be loaded into
the interrupt table.
IRQ Hardware Interrupt request number (0-15).
ISR_Type Specifies if the interrupt function should be treated
as a TRAP_ISR or an INTERRUPT_ISR. Real Mode only