Intel 386 - Manual (Page 166)

7-7
SYSTEM MANAGEMENT MODE
7.3.2.1 SMI# Priority
When more than one exception or interrupt is pending at an instruction boundary, the processor
services them in a predictable order. The priority among classes of exception and interrupt sourc-
es is shown in Table 7-3. The processor first services a pending exception or interrupt from the
class that has the highest priority, transferring execution to the first instruction of the handler.
Lower priority exceptions are discarded; lower priority interrupts are held pending. Discarded ex-
ceptions are reissued when the interrupt handler returns execution to the point of interruption.
SMI# has the following relative priority, where 1 is highest and 11 is lowest:
Table 7-3. Relative Priority of Exceptions and Interrupts
1
(Highest priority)
Double Fault
2 Segmentation Violation
3 Page Fault
4 Divide-by-zero
5 SMI#
6 Single-step
7 Debug
8 ICE Break
9 NMI
10 INTR
11
(Lowest Priority)
I/O Lock