Figure 610. halt cycle, S#. figure 6-10 – Intel 386 User Manual

Page 140

6-27

BUS INTERFACE UNIT

Figure 6-10. Halt Cycle

A2492-02

LOCK#

D15:0

CLK2

BHE#, A1, M/IO#, W/R#

RD#

READY#

Cycle 1

Nonpipelined

(Write)

[Late Ready]

CLKOUT

Cycle 2

Nonpipelined

(Halt)

ADS#

NA#

A25:2, BLE#, D/C#

WR#

LBA#

Idle

Float

Valid 1

CPU remains halted until INTR, SMI#,
NMI, or RESET is asserted.

CPU responds to HOLD input
while in the HALT state.

HALT cycle must be acknowledged by READY# asserted. This READY# could be
generated internally or externally.

Valid 2

†

Out

Undefined

Valid 1