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Intel 386 User Manual

Page 685

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INTEL386™ EX MICROPROCESSOR USER’S MANUAL

Index-6

register locations,

4-5

,

4-15

Peripherals, summary,

2-3

Physical address space,

3-1

Pin configuration,

5-23

PINCFG,

5-24

,

10-23

,

11-17

,

12-31

,

13-17

,

14-15

,

D-46

Pin descriptions,

A-1

A-10

Pin states after reset and during idle, powerdown,

and hold,

A-9

Pipelined instructions, defined,

3-2

Port configuration

P1CFG,

5-25

,

11-18

,

D-43

P2CFG,

5-26

,

11-19

,

14-16

,

D-44

P3CFG,

5-27

,

9-18

,

10-22

,

11-20

,

D-45

PnCFG,

16-7

PnDIR,

16-8

,

D-47

PnLTC,

16-8

,

D-48

PnPIN,

16-9

,

D-48

PORT92,

5-22

,

D-50

PORT92

register addresses,

4-17

,

D-3

Power management

controlling modes,

8-8

,

17-4

17-6

logic,

8-3

8-7

programming

PWRCON,

8-8

,

17-11

,

D-51

register addresses,

4-19

,

D-5

See also Idle mode, powerdown mode, system
management mode

Powerdown mode

considerations,

8-13

SMM interaction with,

8-5

timing diagram,

8-11

Powerup

Built-in self-test,

8-12

JTAG reset,

8-12

Prefetch Queue,

3-4

Priority of exceptions and interrupts,

7-7

Programmed operating mode,

9-8

Programming

chip-select unit,

14-13

14-20

clock and power management unit,

8-7

8-10

DMA controller,

12-28

12-51

ESE bit,

4-8

interrupt control unit,

9-32

RCU,

15-6

15-10

REMAPCFG example,

4-8

serial I/O unit,

11-15

11-32

SSIO,

13-17

13-25

timer/counter unit,

10-20

10-33

watchdog timer unit,

17-7

17-12

Programming considerations

chip-select unit,

14-22

DMA controller,

12-50

serial I/O unit,

11-32

timer/counter unit,

10-33

Protected mode,

9-8

Protection Test Unit,

3-5

PSCLK,

8-1

8-2

,

8-7

,

10-1

,

10-3

,

10-21

,

13-1

,

13-5

,

13-18

PSCLK frequency

Controlling,

8-7

PSRAM,

15-11

R

RAS#-only refresh,

15-1

,

15-12

RCU, See Refresh control unit

Ready logic,

6-10

Real mode,

9-8

Refresh control unit,

15-1

15-16

bus arbitration,

15-5

configuring,

5-3

connections,

15-3

design considerations,

15-11

dynamic memory control,

15-1

operation,

15-5

overview,

15-2

15-5

programming,

15-6

15-10

RFSADD,

15-10

,

D-54

RFSADD register,

15-10

RFSBAD,

15-9

,

D-54

RFSBAD register,

15-9

RFSCIR,

15-7

,

D-55

RFSCIR register,

15-7

RFSCON,

15-8

,

D-55

RFSCON register,

15-8

refresh addresses,

15-4

refresh intervals,

15-4

refresh methods,

15-1