Intel 386 - Manual (Page 46)

3-3
CORE OVERVIEW
Figure 3-2 shows the internal architecture of the Intel386 CX processor.
Figure 3-2. The Intel386™ CX Processor Internal Block Diagram
A2851-02
3-Input
Adder
Descriptor
Register
Limit and
Attribute
PLA
Instruction
Decoder
3 Decoded
Instruction
Queue
Prefetcher
Limit
Checker
16 Byte
Code
Queue
Code
Stream
Barrel
Shifter,
Adder
Multiply/
Divide
Register
File
ALU
Decode
and
Sequencing
Control
ROM
ALU
Control
Protection
Test
Unit
32 Dedicated ALU Bus
32
32
32
Control Instruction
Predecode
Instruction
Prefetch
Linear Address Bus Displacement Bus
Adder
Page
Cache
Control and
Attribute
PLA
MUX/
Transceivers
Pipeline/
Bus Size
Control
Address
Driver
Request
Prioritizer
Internal Control Bus
32
32
Paging Unit
Core Plus
Unit Segmentation Unit
Effective Address Bus
Effective Address Bus
32
32
Physical Address Bus
32
HOLD, INTR, NMI,
ERROR#,BUSY#,
RESET, HLDA,
SMI#, SMIACT#,
PEREQ
BE0#, BE1#,
A25:1
M/IO#, D/C#,
W/R#, LOCK#,
ADS#, NA#,
READY#
D15:0 Code fetch / Page Table Fetch
Control
Status
Flags