Intel 386 User Manual
Page 688
Index-9
INDEX
operation,
13-5
–
13-15
baud-rate generator,
13-5
–
13-6
receiver,
13-12
–
13-15
transmitter,
13-6
overview,
13-1
–
13-4
programming,
13-16
–
13-25
CLKPRS register,
13-19
PINCFG,
13-17
SIOCFG register,
13-18
SSIOBAUD,
13-20
,
D-58
SSIOBAUD register,
13-20
SSIOCON1,
13-22
,
D-59
SSIOCON1 register,
13-21
,
13-22
,
D-59
SSIOCON2 register,
13-23
SSIOCTR,
13-21
,
D-60
SSIOCTR register,
13-21
SSIORBUF,
13-25
,
D-60
SSIORBUF register,
13-25
SSIOTBUF,
13-24
,
D-61
SSIOTBUF register,
13-24
register addresses,
4-18
,
D-4
registers,
13-16
signals,
13-4
SIOCFG,
5-17
,
11-21
,
13-18
,
D-57
System management mode,
2-1
,
7-1
–
7-15
CSU support,
7-12
,
14-10
HALT restart,
7-9
hardware interface,
3-1
,
7-1
SMI#,
7-1
SMIACT#,
7-2
SMRAM state dump area,
7-14
I/O restart,
7-1
identifier registers,
3-6
,
7-15
interaction with idle and powerdown,
8-5
overview,
7-1
priority,
7-7
resume instruction,
7-15
SMI# interrupt,
7-3
,
7-11
–
7-15
during HALT cycle,
7-8
during I/O instruction,
7-9
during SMM handler,
7-10
HALT during SMM handler,
7-11
SMI# during SMM operation,
7-12
SMRAM,
7-2
state dump area,
7-14
–
7-15
System register organization,
4-1
address configuration register,
4-6
address space, I/O for PC/AT systems,
4-2
addressing modes,
4-9
DOS-compatible mode,
4-9
enhanced DOS mode,
4-11
nonDOS mode,
4-11
nonintrusive DOS mode,
4-11
enabling/disabling expanded I/O space,
4-8
expanded I/O address space,
4-3
I/O address decoding techniques,
4-6
organization of peripheral registers,
4-5
overview,
4-1
peripheral register addresses,
4-15
peripheral registers,
4-2
processor core architecture,
4-2
programming
ESE bit,
4-8
REMAPCFG example,
4-8
T
TAP controller,
18-4
TAP Test Access Port,
18-1
TCU, See Timer/counter unit
Technical support,
1-7
Terminology,
1-4
–
1-5
,
Glossary-1
–
Glossary-5
Test access port,
18-1
Test-logic unit, See JTAG test-logic unit
Timer/counter unit,
10-1
–
10-33
configuring,
5-11
hardware triggerable one-shot, See Mode 1
hardware-triggered strobe, See Mode 5
initial count values,
10-26
interrupt on terminal count, See Mode 0
mode 0,
10-6
–
10-8
basic operation,
10-7
disabling the count,
10-7
writing a new count,
10-8
mode 1,
10-8
–
10-10
basic operation,
10-9
retriggering the one-shot,
10-9
writing a new count,
10-10
mode 2,
10-10
–
10-12
basic operation,
10-11
disabling the count,
10-11
writing a new count,
10-12