Intel 386 User Manual
Page 681
INTEL386™ EX MICROPROCESSOR USER’S MANUAL
Index-2
operation during idle mode,
8-5
overview,
6-1
–
6-3
pipelining,
6-8
ready logic,
6-10
See also Bus control arbitration
signals,
6-3
–
6-4
Bus signals, departures from PC/AT
architecture,
B-2
–
B-3
Bus size control for chip-selects,
14-11
BYPASS,
18-2
C
CAS#-before-RAS# refresh,
15-1
,
15-12
Chip-select unit,
14-1–14-24
operation,
14-2
–
14-12
bus cycle length adjustments,
14-12
bus cycle length control,
14-11
bus size control,
14-11
defining a channel’s address block,
14-2
–
14-9
overlapping regions,
14-11
system management mode support,
14-10
overview,
14-1
programming,
14-13
–
14-20
considerations,
14-22
CSnADH,
14-17
,
D-8
CSnADL,
14-18
,
D-9
CSnMSKH,
14-19
,
D-10
CSnMSKL,
14-20
,
D-11
P2CFG register,
14-16
PINCFG register,
14-15
UCSADH,
14-17
,
D-8
UCSADL,
14-18
,
D-9
UCSMSKH,
14-19
,
D-10
UCSMSKL,
14-20
,
D-11
register addresses,
4-17
,
D-3
registers,
14-14
–
14-20
signals,
14-13
Clear, defined,
1-5
Clock and power management unit,
8-1
–
8-13
clock generation logic,
8-1
–
8-3
controlling power management modes,
8-8
controlling PSCLK frequency,
8-7
design considerations
powerdown considerations,
8-13
reset considerations,
8-11
idle mode,
8-9
overview,
8-1
–
8-7
power management logic,
8-3
–
8-5
powerdown mode,
8-10
registers,
8-6
CLKPRS,
8-7
PWRCON,
8-8
reset considerations,
8-11
signals,
8-6
synchronization,
8-3
timing diagram,
8-9
–
8-11
Clock management
register addresses,
4-19
,
D-5
Clock synchronization,
8-3
Code Prefetch Unit,
3-4
CompuServe forums,
1-7
Configuration
bus arbiter,
5-3
–
5-5
core,
5-21
–
5-22
device,
5-1
–
5-37
DMA controller,
5-3
example,
5-28
–
5-33
I/O ports,
5-23
,
5-25
,
5-26
,
5-27
,
9-18
,
10-22
,
11-18
,
11-19
,
11-20
,
14-16
,
D-43
,
D-44
,
D-45
interrupt control unit,
5-7
pins,
5-23
–
5-27
Port92,
5-22
procedure,
5-28
refresh control unit,
5-3
serial I/O unit,
5-14
serial synchronous I/O unit,
5-18
timer/counter unit,
5-11
worksheets,
5-34
–
5-37
Core
configuring,
5-21
–
5-22
Core architecture,
2-1
Core overview
CX enhancements,
3-1
Internal architecture,
3-2
CPU-only reset,
5-22
,
B-4
CSU, See Chip-select unit
Customer service,
1-6
CX internal architecture,
3-2