Intel 386 - Manual (Page 590)

D-25
SYSTEM REGISTER QUICK REFERENCE
D.20 DMAOVFE
DMA Overflow Enable
DMAOVFE
(read/write) Expanded Addr:
ISA Addr:
Reset State: F01DH
—
0AH
7 0
— — — — ROV1 TOV1 ROV0 TOV0
Bit
Number
Bit
Mnemonic
Function
7–4 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
3 ROV1 Channel 1 Requester Overflow Enable:
0 = lowest 16 bits of requester address increment/decrement
1 = all bits of requester address increment/decrement
2 TOV1 Channel 1 Target & Byte Counter Overflow Enable:
0 = lowest 16 bits of target address and byte count
increment/decrement
1 = all bits of target address and byte count increment/decrement
1 ROV0 Channel 0 Requester Overflow Enable:
0 = lowest 16 bits of requester address increment/decrement
1 = all bits of requester address increment/decrement
0 TOV0 Channel 0 Target & Byte Counter Overflow Enable:
0 = lowest 16 bits of target address and byte count
increment/decrement
1 = all bits of target address and byte count increment/decrement