6 status register (dmasts), Figure 1223. dma status register (dmasts) – Intel 386 User Manual
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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
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12.3.6 Status Register (DMASTS)
Use DMASTS to check the status of the channels individually. The DMA sets bits in this register
to indicate that a channel has a hardware request pending or that a channel’s byte count has ex-
pired.
Figure 12-23. DMA Status Register (DMASTS)
DMA Status
DMASTS
(read only)
Expanded Addr:
ISA Addr:
Reset State:
F008H
0008H
00H
7
0
—
—
R1
R0
—
—
TC1
TC0
Bit
Number
Bit
Mnemonic
Function
7–6
—
Reserved. These bits are undefined.
5
R1
Request 1:
When set, this bit indicates that channel 1 has a hardware request
pending. When the request is removed, this bit is cleared.
4
R0
Request 0:
When set, this bit indicates that channel 0 has a hardware request
pending. When the request is removed, this bit is cleared.
3–2
—
Reserved. These bits are undefined.
1
TC1
Transfer Complete 1:
When set, this bit indicates that channel 1 has completed a buffer
transfer (either its byte count expired or it received an EOP# input).
Reading this register clears this bit and clears TC1 in DMAIS.
0
TC0
Transfer Complete 0:
When set, this bit indicates that channel 0 has completed a buffer
transfer (either its byte count expired or it received an EOP# input).
Reading this register clears this bit and clears TC0 in DMAIS.