Intel 386 User Manual

Page 683

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INTEL386™ EX MICROPROCESSOR USER’S MANUAL

Index-4

DOS compatibility

departures from PC/AT architecture

bus signals,

B-2

CPU-only reset,

B-4

DMA unit,

B-1

HOLD, HLDA pins,

B-4

,

B-5

interrupt control unit,

B-4

SIO units,

B-4

DRAM, refreshing,

15-12

DRAM, See Refresh control unit

E

EISA compatibility,

4-3

–

4-5

ESE bit programming,

4-8

Exceptions and interrupts, relative priority,

7-7

Execution Unit,

3-4

,

3-5

Expanded address, defined,

1-4

Expanded I/O address space,

4-3

enabling/disabling,

4-8

F

FaxBack service,

1-6

Flow diagram

CSU bus cycle length adjustment,

14-12

demand data-transfer mode,

12-22

–

12-24

DMA block data-transfer mode,

12-19

–

12-20

DMA cascade mode,

12-26

DMA demand data-transfer mode,

12-22

DMA single data-transfer mode,

12-15

–

12-17

interrupt process,

9-11

,

9-12

,

9-13

SIO reception,

11-11

SIO transmission,

11-8

H

HALT cycle

Ready generation,

8-10

HALT restart from SMM,

7-9

HOLD, HLDA

departures from PC/AT architecture,

B-4

,

B-5

timing,

6-20

,

6-35

I

I/O ports, See Input/output ports

I/O restart from SMM,

7-9

ICU, See Interrupt control unit

IDCODE,

18-2

Identifier registers,

3-6

,

7-15

Idle mode,

8-9

bus interface unit operation during,

8-5

SMM interaction with,

8-5

timing diagram,

8-9

watchdog timer unit operation during,

8-5

IEEE Standard Test Access Port and

Boundary-Scan Architecture,

18-1

Input/output ports,

16-1

–

16-10

block diagram,

16-2

design considerations,

16-10

overview,

16-1

–

16-5

pin multiplexing,

16-5

pin reset status,

16-5

programming

initialization sequence,

16-10

pin configuration,

16-7

PnCFG register,

16-7

PnDIR register,

16-8

PnLTC register,

16-8

PnPIN register,

16-9

register addresses,

4-19

,

D-5

registers,

16-6

signals,

16-5

Instruction Decode Unit,

3-4

Instruction Queue,

3-5

Instruction Register (IR),

18-7

Instructions, notational conventions,

1-3

Interrupt control unit,

9-1

–

9-30

configuring,

5-7

departure from PC/AT architecture,

B-4

design considerations,

9-29

interrupt acknowledge cycle,

9-29

–

9-30

interrupt detection,

9-29

interrupt polling,

9-14

–

9-15

interrupt priority,

9-6

–

9-8

assigning an interrupt level,

9-6

changing the default interrupt structure,

9-7

determining priority,

9-7

–

9-8

interrupt process,

9-9

–

9-14

interrupt sources,

9-4

interrupt service routine,

6-23

interrupt vectors,

9-8