Index – Intel 386 User Manual
Page 680
Index-1
#, defined,
1-3
82C59A,
9-1
A
Address bus,
6-1
Address lines
new,
3-1
Address space
configuration register,
4-6
expanded I/O,
4-3
enabling/disabling,
4-8
I/O decoding techniques,
4-6
I/O for PC/AT systems,
4-2
peripheral registers,
4-15
Addressing modes,
4-9
–
4-14
DOS-compatible mode,
4-9
–
4-10
enhanced DOS mode,
4-11
,
4-13
nonDOS mode,
4-11
,
4-14
nonintrusive DOS mode,
4-11
,
4-12
AEN signal, deriving,
B-2
–
B-3
AEOI mode,
9-9
aligned data transfers,
6-9
Applications, typical,
2-1
Architectural overview,
2-1
–
2-4
Assert, defined,
1-4
Asynchronous serial I/O unit, See Serial I/O unit
Automatic end of interrupt (AEOI) mode,
9-9
B
Baud-rate generator,
11-4
–
11-5
,
13-5
–
13-6
BIU, See Bus interface unit
Block diagram
clock and power management unit,
8-2
DMA unit,
12-2
I/O port,
16-2
JTAG test-logic unit,
18-2
SIO unit,
11-2
baud-rate generator clock,
11-4
modem control signals,
11-29
receiver,
11-9
transmitter,
11-7
SSIO unit,
13-2
,
13-3
baud-rate generator clock,
13-5
timer/counter unit,
10-2
watchdog timer unit,
17-2
BOUND,
18-2
Boundary scan register,
18-1
Built-in self-test,
8-12
Bulletin board system (BBS),
1-7
Bus arbiter
register addresses,
4-15
,
D-1
Bus arbiter, configuration,
5-3
Bus control arbitration,
12-9
Bus cycle length adjustments for overlapping
chip-select regions,
14-11
,
14-12
Bus interface pins,
6-3
Bus interface unit,
3-4, 6-1
–
6-37
address bus,
6-1
bus control pins,
6-2
bus cycles,
6-13
–
6-33
BS8,
6-31
–
6-33
halt/shutdown,
6-26
–
6-27
interrupt acknowledge,
6-23
–
6-25
pipelined,
6-19
–
6-23
read,
6-13
–
6-14
refresh,
6-28
–
6-30
write,
6-16
–
6-18
bus lock,
6-34
–
6-35
LOCK# signal duration,
6-35
locked cycle activators,
6-34
locked cycle timing,
6-34
bus operation,
6-5
–
6-14
bus state diagram,
6-8
,
6-20
bus states,
6-7
–
6-8
bus status
definitions,
6-5
data bus,
6-1
transfers and operand alignment,
6-9
HOLD/HLDA,
6-20
,
6-35
departures from PC/AT architecture,
B-4
HOLD signal latency,
6-37
timing,
6-36
INDEX