Intel 386 - Manual (Page 232)

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INTERRUPT CONTROL UNIT
BYTE _CascadeBits_ = 0x4;
/*****************************************************************************
InitICU
Description:
Initialization for both the master and slave Interrupt Control
Units (ICU). tine only initializes the internal interrupt
controllers, external ICUs must be initialized separately. These
should be initialized before interrupts are enabled(i.e., enable()).
Parameters:
MstrMode Mode of operation for Master ICU
MstrBase Specifies the base interrupt vector number for the
Master interrupts.
For example, if IR1 of the master goes active and the
MstrBase = 0x20, the processor uses interrupt
vector table entry 0x21.
MstrCascade Which Master IRQs are used for Slave ICUs.
SlaveMode Mode of operation for Slave ICU
SlaveBase Specifies the base interrupt vector number for the
Slave interrupts.
For example, if IR1 of the slave goes active and the
SlaveBase = 0x40, the processor uses interrupt
vector table entry 0x41.
MstrPins Defines what EX pins are available externally to the
chip for the Master.
SlavePins Defines what EX pins are available externally to the
chip for the Slave.
Returns:Error Code
E_OK -- Initialized OK, No error.
Assumptions:
REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
Syntax:
#define ICU_TRIGGER_EDGE 0x0
#define MPIN_INT0 0x4
#define MCAS_IR1 0x2
#define SPIN_INT4 0x1
int error_code;
error_code = InitICU(ICU_TRIGGER_EDGE,
0x20,
MCAS_IR1,
ICU_TRIGGER_EDGE,
0x30,
MPIN_INT0,
SPIN_INT4);