Intel 386 - Manual (Page 469)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
15-8
15.4.2 Refresh Control Register (RFSCON)
Use RFSCON to enable and disable the refresh control unit and to check the current interval
counter value.
Figure 15-3. Refresh Control Register (RFSCON)
Refresh Control
RFSCON
(read/write) Expanded Addr:
ISA Addr:
Reset State: F4A4H
—
0000H
15 8
REN — — — — — CV9 CV8
7 0
CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0
Bit
Number
Bit
Mnemonic
Function
15 REN Refresh Control Unit Enable:
This bit enables or disables the refresh control unit.
0 = Disables refresh control unit
1 = Enables refresh control unit
14–10 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
9–0 CV9:0 Counter Value:
These read-only bits represent the current value of the interval counter.
Write operations to these bits have no effect.