Epson ARM.POWERED ARM720T - Manual (Page 99)

7: Memory Management Unit
ARM720T CORE CPU MANUAL EPSON 7-3
7.2 MMU program-accessible registers
Table 7-1 lists the CP15 registers that are used in conjunction with page table descriptors
stored in memory to determine the operation of the MMU.
All the CP15 MMU registers, except register c8, contain state. You can read them using MRC
instructions, and write to them using MCR instructions. Registers c5 and c6 are also written
by the MMU during all aborts. Writing to register c8 causes the MMU to perform a TLB
operation, to manipulate TLB entries. This register cannot be read.
CP15 is described in Chapter 3
Configuration , with details of register formats and the
coprocessor instructions you can use to access them.
Table 7-1 CP15 register functions
Register Number Bits Register description
Control register 1 M, A, S, R Contains bits to enable the MMU (M bit), enable data
address alignment checks (A bit), and to control the
access protection scheme (S bit and R bit).
Translation
Table Base
Register 2 31:14 Holds the physical address of the base of the translation
table maintained in main memory. This base address must
be on a 16KB boundary.
Domain Access
Control
Register 3 31:0 Comprises 16 2-bit fields. Each field defines the access
control attributes for one of 16 domains (D15–D0).
Fault Status
Register 5 7:0 Indicates the cause of a Data or Prefetch Abort, and the
domain number of the aborted access, when an abort
occurs. Bits 7:4 specify which of the 16 domains (D15–D0)
was being accessed when a fault occurred. Bits 3:0
indicate the type of access being attempted. The value of
all other bits is Unpredictable. The encoding of these bits
is shown in Table 7-9 on page 7-16.
Fault Address
Register 6 31:0 Holds the MVA associated with the access that caused the
abort. See Table 7-9 on page 7-16 for details of the
address stored for each type of fault.
You can use banked register c14 to determine the VA
associated with a Prefetch Abort.
TLB Operations
Register 8 31:0 You can write to this register to make the MMU perform
TLB maintenance operations. These are:
• invalidating all the entries in the TLB
• invalidating a specific entry.