Epson ARM.POWERED ARM720T - Manual (Page 68)

3: Configuration
3-8 EPSON ARM720T CORE CPU MANUAL
In the instructions shown in Table 3-3, c7 is the preferred value for the CRn field, because it
indicates a unified MMU.
Reading from CP15 Register 8 is undefined.
The Invalidate TLB single entry function invalidates any TLB entry corresponding to the
Modified Virtual Address (MVA) given in Rd.
3.3.9 Process Identifier Registers
You can access two independent process identifier registers using Register 13:
• Fast Context Switch Extension Process Identifier Register
• Trace Process Identifier Register on page 3-8.
Fast Context Switch Extension Process Identifier Register
Reading from CP15 Register 13 with opcode_2 = 0 returns the value of the Fast Context Switch
Extension (FCSE) Process IDentifier (PID). FCSCE PID Register format is shown in
Figure 3-10.
Figure 3-10 FCSCE PID Register format
Note:
Only bits [31:25] are returned. The remaining 25 bits are Unpredictable.
Writing to CP15 Register 13 with opcode_2 = 0 updates the FCSE PID from the value in bits
[31:25]. Bits [24:0] Should Be Zero. The FCSE PID is set to b0000000 on Reset.
The CRm and opcode_2 Should Be Zero when reading or writing the FCSE PID.
Changing FCSE PID
You must take care when changing the FCSE PID because the following instructions have
been fetched with the previous FCSE PID. In this way, changing the FCSE PID has
similarities with a branch with delayed execution. See Relocation of low virtual addresses by
the FCSE PID on page 2-15.
Trace Process Identifier Register
A 32-bit read/write register is provided to hold a Trace PROCess IDentifier (PROCID) up to
32-bits in length visible to the ETM7. This is achieved by reading from or writing to the
PROCID Register with opcode_2 set to 1. PROCID Register format is shown in Figure 3-11.
Figure 3-11 PROCID Register format
The PROCIDWR signal is exported to notify the ETM7 that the Trace PROCID has been
written.
31 25 24 00
FCSE PID UNP/SBZ
31 00
Trace PROCID