Epson ARM.POWERED ARM720T - Manual (Page 74)

4: Instruction and Data Cache
4-2 EPSON ARM720T CORE CPU MANUAL
4.1.3 Read-lock-write
The IDC treats the read-lock-write instruction as a special case:
Read phase Always forces a read of external memory, regardless of whether the
data is contained in the cache.
Write phase Is treated as a normal write operation. If the data is already in the
cache, the cache is updated.
Externally, the two phases are flagged as indivisible by asserting the HLOCK signal.
4.2 IDC validity
The IDC operates with virtual addresses, so you must ensure that its contents remain
consistent with the virtual to physical mappings performed by the MMU. If the memory
mappings are changed, the IDC validity must be ensured.
4.2.1 Software IDC flush
The entire IDC can be marked as invalid by writing to the Cache Operations Register c7. The
cache is flushed immediately the register is written, but the following two instruction fetches
can come from the cache before the register is written.
4.2.2 Doubly-mapped space
Because the cache works with virtual addresses, it is assumed that every virtual address maps
to a different physical address. If the same physical location is accessed by more than one
virtual address, the cache cannot maintain consistency. Each virtual address has a separate
entry in the cache, and only one entry can be updated on a processor write operation.
To avoid any cache inconsistencies, both doubly-mapped virtual addresses must be marked as
uncachable.
4.3 IDC enable, disable, and reset
The IDC is automatically disabled and flushed on HRESETn. When enabled, cachable read
accesses cause lines to be placed in the cache.
To enable the IDC:
1 Make sure that the MMU is enabled first by setting bit 0 in the Control Register.
2 Enable the IDC by setting bit 2 in the Control Register. The MMU and IDC can be
enabled simultaneously with a single write to the Control Register.
To disable the IDC:
1 Clear bit 2 in the Control Register.
2 Perform a flush by writing to the cache operations register.