Epson ARM.POWERED ARM720T - Manual (Page 130)

8: Coprocessor Interface
8-10 EPSON ARM720T CORE CPU MANUAL
8.6 Not using an external coprocessor
If you are implementing a system that does not include any external coprocessors, you must
tie both EXTCPA and EXTCPB HIGH. This indicates that no external coprocessors are
present in the system. If any coprocessor instructions are received, they take the undefined
instruction trap so that they can be emulated in software if required.
The coprocessor-specific outputs from the ARM720T core can be left unconnected:
• CPnMREQ
• CPnTRANS
• CPnOPC
• CPnCPI
• CPTBIT.
You must tie off EXTCPDOUT.
You must tie the external coprocessor data bus enable, EXTCPDBE, LOW.
8.7 STC operations
If you are using an external coprocessor, you can perform STC operations in cachable regions
with the cache enabled. However, the STC operation is treated as a series of nonsequential
transfers on the AMBA bus.
8.8 Undefined instructions
The ARM720T processor implements full ARM architecture v4T undefined instruction
handling. This means that any instruction defined in the ARM Architecture Reference Manual
as UNDEFINED, automatically causes the ARM720T processor to take the undefined
instruction trap. Any coprocessor instructions that are not accepted by a coprocessor also
result in the ARM720T processor taking the undefined instruction trap.
8.9 Privileged instructions
The output signal CPnTRANS enables you to implement coprocessors, or coprocessor
instructions, that can only be accessed from privileged modes. The signal meanings are shown
in Table 8-4.
The CPnTRANS signal is sampled at the same time as the instruction, and is factored into the
coprocessor pipeline Decode stage.
Note:
If a User-mode process (CPnTRANS LOW) tries to access a coprocessor instruction
that can only be executed in a privileged mode, the coprocessor must respond with
EXTCPA and EXTCPB HIGH. This causes the ARM720T processor to take the
undefined instruction trap.
Table 8-4 CPnTRANS signal meanings
CPnTRANS Meaning
LOW User mode instruction
HIGH Privileged mode instruction