Epson ARM.POWERED ARM720T - Manual (Page 10)

CONTENTS
vi EPSON ARM720T CORE CPU MANUAL
List of Tables
Table 1-1 Key to tables ............................................................................................... 1-6
Table 1-2 ARM instruction summary ........................................................................... 1-8
Table 1-3 Addressing mode 2 ................................................................................... 1-10
Table 1-4 Addressing mode 2 (privileged) ................................................................ 1-11
Table 1-5 Addressing mode 3 ................................................................................... 1-11
Table 1-6 Addressing mode 4 (load) ......................................................................... 1-11
Table 1-7 Addressing mode 4 (store) ........................................................................ 1-12
Table 1-8 Addressing mode 5 ................................................................................... 1-12
Table 1-9 Operand 2 ................................................................................................. 1-12
Table 1-10 Fields......................................................................................................... 1-12
Table 1-11 Condition fields.......................................................................................... 1-13
Table 1-12 Thumb instruction summary ...................................................................... 1-15
Table 2-1 ARM720T modes of operation .................................................................... 2-4
Table 2-2 PSR mode bit values................................................................................... 2-9
Table 2-3 Exception entry and exit ............................................................................ 2-11
Table 2-4 Exception vector addresses ...................................................................... 2-13
Table 3-1 Cache and MMU Control Register .............................................................. 3-3
Table 3-2 Cache operation .......................................................................................... 3-7
Table 3-3 TLB operations ............................................................................................ 3-7
Table 6-1 Transfer type encoding ............................................................................... 6-5
Table 6-2 Transfer size encodings .............................................................................. 6-7
Table 6-3 Burst type encodings................................................................................... 6-8
Table 6-4 Protection control encodings ....................................................................... 6-8
Table 6-5 Response encodings................................................................................. 6-10
Table 6-6 Active byte lanes for a 32-bit little-endian data bus................................... 6-11
Table 6-7 Active byte lanes for a 32-bit big-endian data bus .................................... 6-12
Table 7-1 CP15 register functions ............................................................................... 7-3
Table 7-2 Level one descriptor bits ............................................................................. 7-7
Table 7-3 Interpreting level one descriptor bits [1:0] ................................................... 7-7
Table 7-4 Section descriptor bits ................................................................................. 7-8
Table 7-5 Coarse page table descriptor bits ............................................................... 7-9
Table 7-6 Fine page table descriptor bits .................................................................... 7-9
Table 7-7 Level two descriptor bits............................................................................ 7-11
Table 7-8 Interpreting page table entry bits [1:0]....................................................... 7-11
Table 7-9 Priority encoding of fault status ................................................................. 7-16
Table 7-10 Interpreting access control bits in Domain Access Control Register......... 7-17
Table 7-11 Interpreting access permission (AP) bits................................................... 7-18
Table 8-1 Coprocessor availability .............................................................................. 8-2
Table 8-2 Handshaking signals ................................................................................... 8-5
Table 8-3 Handshake signal connections ................................................................... 8-9
Table 8-4 CPnTRANS signal meanings .................................................................... 8-10
Table 9-1 Function and mapping of EmbeddedICE-RT registers ............................. 9-12
Table 9-2 Domain Access Control Register bit assignments .................................... 9-15
Table 9-3 Instruction encodings for scan chain 15 .................................................... 9-18
Table 9-4 Public instructions ..................................................................................... 9-20
Table 9-5 Scan chain number allocation ................................................................... 9-23
Table 9-6 Scan chain 1 cells ..................................................................................... 9-25