Epson ARM.POWERED ARM720T - Manual (Page 30)

1: Introduction
1-10 EPSON ARM720T CORE CPU MANUAL
Addressing mode 2, , is shown in Table 1-3.
Coprocessors Data operations CDP{cond} p, , , ,
,
Move to ARM reg from coproc MRC{cond} p, , , ,
,
Move to coproc from ARM reg MCR{cond} p, , , ,
,
Load LDC{cond} p, ,
Store STC{cond} p, ,
Software
Interrupt SWI <24bit_Imm>
Table 1-3 Addressing mode 2
Operation Assembler
Immediate offset [, #+/-<12bit_Offset>]
Register offset [, +/-]
Scaled register offset [, +/-, LSL #<5bit_shift_imm>]
[, +/-, LSR #<5bit_shift_imm>]
[, +/-, ASR #<5bit_shift_imm>]
[, +/-, ROR #<5bit_shift_imm>]
[, +/-, RRX]
Pre-indexed immediate offset [, #+/-<12bit_Offset>]!
Pre-indexed register offset [, +/-]!
Pre-indexed scaled register offset [, +/-, LSL #<5bit_shift_imm>]!
[, +/-, LSR #<5bit_shift_imm>]!
[, +/-, ASR #<5bit_shift_imm>]!
[, +/-, ROR #<5bit_shift_imm>]!
[, +/-, RRX]!
Post-indexed immediate offset [], #+/-<12bit_Offset>
Post-indexed register offset [], +/-
Post-indexed scaled register offset [], +/-, LSL #<5bit_shift_imm>
[], +/-, LSR #<5bit_shift_imm>
[], +/-, ASR #<5bit_shift_imm>
[], +/-, ROR #<5bit_shift_imm>
[, +/-, RRX]
Table 1-2 ARM instruction summary (continued)
Operation Assembler