Epson ARM.POWERED ARM720T - Manual (Page 191)

11: Test Support
ARM720T CORE CPU MANUAL EPSON 11-7
Example 11-1 shows sample code for performing software test of the cache. It contains typical
operations with register C15.C.
Example 11-1 Cache test operations
; CAM write, read and check for segment 2
; Write cache victim pointer with index 0, segment 2
MOV r0,#0
ORR r1,r0,#2 :SHL: 0x5
MCR p15,0,r1,c9,c1,0
; Write pattern in 0xFFFFFF9E in all 64 CAM lines
MVN r2,#1 ; bit 0 should be ‘0’
BIC r2,r2,#0x20 ; write segment 2
MOV r8,#64
loop0 MCR p15,2,r2,c15,c7,6 ; write CAM, index auto-incremented
SUBS r8,r8,#1
BNE loop0
; Now read and check
; Reset victim pointer to index 0, segment 2
MOV r0,#0
ORR r1,r0,#2 :SHL:0x5
MCR p15,0,r1,c9,c1,0
MOV r8,#64
MOV r3,#0x40
; read segment 2
BIC r2,r2,#0x60 ; clear bit 5 and 6 (always read as ‘0’)
loop1 MCR p15,3,r0,c15,c3,0 ; write C15.C to ‘0’
MCR p15,2,r3,c15,c7,2 ; read CAM to C15.C
MRC p15,3,r4,c15,c3,0 ; read C15.C to R4
BIC r4,r4,#1 ; clear LFSR bit
CMP r4,r2
BNE TEST_FAIL
SUBS r8,r8,#1
BNE loop1
B TEST_PASS
; RAM write, read and check for segment 1
; Write cache victim pointer with index 0, segment 1
MOV r0,#0
ORR r1,r0,#1 :SHL: 0x5
MCR p15,0,r1,c9,c1,0
; Write pattern 0x5A5A5A5A in RAM line (eight words)
LDR r0,=0x5A5A5A5A
MOV r8,#8
MOV r2,#0x10
;write segment 1,word 0
MCR p15,3,r0,c15,c3,0 ; write RAM data in C15.C
loop0 MCR p15,2,r2,c15,c11,6 ; write RAM
ADD r2,r2,#0x04 ; next word
SUBS r8,r8,#1
BNE loop0