Epson ARM.POWERED ARM720T - Manual (Page 159)

9: Debugging Your System
ARM720T CORE CPU MANUAL EPSON 9-27
9.16.1 Determining the core state
When the processor has entered debug state from Thumb state, the simplest course of action
is for the debugger to force the core back into ARM state. The debugger can then execute the
same sequence of instructions to determine the processor state.
To force the processor into ARM state, execute the following sequence of Thumb instructions
on the core:
STR R0, [R0] ; Save R0 before use
MOV R0, PC ; Copy PC into R0
STR R0, [R0] ; Now save the PC in R0
BX PC ; Jump into ARM state
MOV R8, R8 ; NOP
MOV R8, R8 ; NOP
Note:
Because all Thumb instructions are only 16 bits long, you can repeat the instruction
when shifting scan chain 1. For example, the encoding for BX R0 is 0x4700, so when
0x47004700
shifts into scan chain 1, the debugger does not have to keep track of the
half of the bus on which the processor expects to read the data.
You can use the sequences of ARM instructions below to determine the state of the processor.
With the processor in the ARM state, the first instruction to execute is typically:
STM R0, {r0-r15}
This instruction causes the contents of the registers to appear on the data bus. You can then
sample and shift out these values.
Note:
The use of r0 as the base register for the STM is only for illustration, any register
can be used.
After you have determined the values in the current bank of registers, you might wish to
access the banked registers. To do this, you must change mode. Normally, a mode change can
occur only if the core is already in a privileged mode. However, while in debug state, a mode
change from one mode into any other mode can occur.
The debugger must restore the original mode before exiting debug state. For example, if the
debugger was requested to return the state of the User mode registers, and FIQ mode
registers, and debug state was entered in Supervisor mode, the instruction sequence might be:
STM R0, {r0-r15} ; Save current registers
MRS R0, CPSR
STR R0, R0 ; Save CPSR to determine current mode
BIC R0, 0x1F ; Clear mode bits
ORR R0, 0x10 ; Select user mode
MSR CPSR, R0 ; Enter USER mode
STM R0, {r13,r14} ; Save register not previously visible
ORR R0, 0x01 ; Select FIQ mode
MSR CPSR, R0 ; Enter FIQ mode
STM R0, {r8-r14} ; Save banked FIQ registers