Epson ARM.POWERED ARM720T - Manual (Page 143)

9: Debugging Your System
ARM720T CORE CPU MANUAL EPSON 9-11
Abort status register
This register identifies whether an abort exception entry was
caused by a breakpoint, a watchpoint, or a real abort. For more
information, see Abort status register on page 9-38.
Debug Communications Channel (DCC)
The DCC passes information between the target and the host
debugger. For more information, see The debug communications
channel on page 9-14.
In addition, two independent registers provide overall control of EmbeddedICE-RT operation.
These are described in the following sections:
• Debug control register on page 9-39
• Debug status register on page 9-41.
The locations of the EmbeddedICE-RT registers are given in EmbeddedICE-RT timing on
page 9-44.
9.7 Disabling EmbeddedICE-RT
You can disable EmbeddedICE-RT in two ways:
Permanently By wiring the DBGEN input LOW.
When DBGEN is LOW:
•
DBGBREAK and DBGRQ are ignored by the core
Note:
DBGACK is forced LOW by the ARM720T core
• interrupts pass through to the processor uninhibited
• the EmbeddedICE-RT logic enters low-power mode.
Caution:
Hard-wiring the DBGEN input LOW permanently
disables debug state information. However, you must
not rely on this for system security.
Temporarily By setting bit 5 in the Debug Control Register (described in Debug
control register on page 9-39). Bit 5 is also known as the
EmbeddedICE-RT disable bit.
You must set bit 5 before doing either of the following:
•
programming breakpoint or watchpoint registers
• changing bit 4 of the Debug Control Register.