Epson ARM.POWERED ARM720T - Manual (Page 141)

9: Debugging Your System
ARM720T CORE CPU MANUAL EPSON 9-9
9.4 Debug interface
The ARM720T processor debug interface is based on IEEE Std. 1149.1- 1990, Standard Test
Access Port and Boundary-Scan Architecture . Refer to this standard for an explanation of the
terms used in this chapter, and for a description of the TAP controller states.
9.4.1 Debug interface signals
There are three primary external signals associated with the debug interface:
• DBGBREAK and DBGRQ are system requests for the ARM720T core to enter
debug state
Note:
Both DBGRQ and DBGBREAK must be LOW when the core has entered debug
state. If they are not, these signals affect the use of the DBGBREAK flag on scan
chain 1, which controls the way the core goes into and out of debug. The result is
that the core performs an unexpected series of debug and system speed accesses,
and the debugger loses control of the core.
• DBGACK is used by the ARM720T core to flag back to the system that it is in debug
state.
9.5 ARM720T core clock domains
The ARM720T processor has a single clock, HCLK, that is qualified by two clock enables:
• HCLKEN controls access to the memory system
• DBGTCKEN controls debug operations.
When the ARM720T processor is in debug state, DBGTCKEN conditions HCLK to clock the
core.