Epson ARM.POWERED ARM720T - Manual (Page 37)

1: Introduction
ARM720T CORE CPU MANUAL EPSON 1-17
Note:
All thumb fetches are done as 32-bit bus transactions using the 32-bit thumb
prefetch buffer.
Load With register offset
word LDR , [, ]
halfword LDRH , [, ]
signed halfword LDRSH , [, ]
byte LDRB , [, ]
signed byte LDRSB , [, ]
PC-relative LDR , [PC, #<10bit_offset>]
SP-relative LDR , [SP, #<10bit_offset>]
Address
using PC ADD , PC, #<10bit_offset>
using SP ADD , SP, #<10bit_offset>
Multiple LDMIA Rb!,
Store With immediate offset
word STR , [, #<7bit_offset>]
halfword STRH , [, #<6bit_offset>]
byte STRB , [, #<5bit_offset>]
With register offset
word STR , [, ]
halfword STRH , [, ]
byte STRB , [, ]
SP-relative STR , [SP, #<10bit_offset>]
Multiple STMIA !,
Push/Pop Push registers onto stack PUSH
Push LR, and registers
onto stack PUSH
Pop registers from stack POP
Pop registers, and PC
from stack POP
Software
Interrupt SWI <8bit_Imm>
Table 1-12 Thumb instruction summary (continued)
Operation Assembler