Epson ARM.POWERED ARM720T - Manual (Page 89)

6: The Bus Interface
ARM720T CORE CPU MANUAL EPSON 6-9
6.5 Slave transfer response signals
After a master has started a transfer, the slave determines how the transfer progresses. No
provision is made in the AHB specification for a bus master to cancel a transfer after it has
begun.
Whenever a slave is accessed it must provide a response using the following signals:
HRESP[1:0] Indicates the status of the transfer.
HREADY Used to extend the transfer. This signal works in combination with
HRESP[1:0].
The slave can complete the transfer in a number of ways. It can:
• complete the transfer immediately
• insert one or more wait states to enable time to complete the transfer
• signal an error to indicate that the transfer has failed
• delay the completion of the transfer, but enable the master and slave to back off the
bus, leaving it available for other transfers.
6.5.1 HREADY
The HREADY signal is used to extend the data portion of an AHB transfer, as follows:
HREADY LOW Indicates that the transfer data is to be extended. It causes wait
states to be inserted into the transfer and enables extra time for
the slave to provide or sample data.
HREADY HIGH Indicates that the transfer can complete.
Every slave must have a predetermined maximum number of wait states that it inserts before
it backs off the bus, in order to enable the calculation of the latency of accessing the bus. To
prevent any single access locking the bus for a large number of clock cycles, it is recommended
that slaves do not insert more than 16 wait states.