Epson ARM.POWERED ARM720T - Manual (Page 111)

7: Memory Management Unit
ARM720T CORE CPU MANUAL EPSON 7-15
7.4 MMU faults and CPU aborts
The MMU generates an abort on the following types of faults:
• alignment faults (data accesses only)
• translation faults
• domain faults
• permission faults.
In addition, an external abort can be raised by the external system. This can happen only for
access types that have the core synchronized to the external system:
• noncachable loads
• nonbufferable writes.
Alignment fault checking is enabled by the A bit in CP15 register c1. Alignment fault checking
is not affected by whether or not the MMU is enabled. Translation, domain, and permission
faults are only generated when the MMU is enabled.
The access control mechanisms of the MMU detect the conditions that produce these faults. If
a fault is detected as a result of a memory access, the MMU aborts the access and signals the
fault condition to the CPU core. The MMU retains status and address information about faults
generated by the data accesses in the Fault Status Register and Fault Address Register (see
Fault address and fault status registers on page 7-16).
An access violation for a given memory access inhibits any corresponding external access, with
an abort returned to the CPU core.