Epson ARM.POWERED ARM720T User Manual
Arm720t revision 4, Core cpu manual, Amba ahb bus interface version)
ARM720T Revision 4
(AMBA AHB Bus Interface Version)
CORE CPU MANUAL
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
http://www.epsondevice.com
Issue April, 2004
Printed in Japan
C
A
Document code: 405003400
CORE CPU MANUAL
ARM720T Revision 4
(AMBA AHB Bus Interface Version)
CORE CPU MANUAL
ARM720T Revision 4
(AMBA AHB Bus Interface Version)
Table of contents
Document Outline
- Contents
- Preface
- 1 Introduction
- 2 Programmer’s Model
- 2.1 Processor operating states
- 2.2 Memory formats
- 2.3 Instruction length
- 2.4 Data types
- 2.5 Operating modes
- 2.6 Registers
- 2.7 Program status registers
- 2.8 Exceptions
- 2.8.1 Action on entering an exception
- 2.8.2 Action on leaving an exception
- 2.8.3 Exception entry and exit summary
- 2.8.4 Fast interrupt request
- 2.8.5 Interrupt request
- 2.8.6 Abort
- 2.8.7 Software interrupt
- 2.8.8 Undefined instruction
- 2.8.9 Exception vectors
- 2.8.10 Exception priorities
- 2.8.11 Exception restrictions
- 2.9 Relocation of low virtual addresses by the FCSE PID
- 2.10 Reset
- 2.11 Implementation-defined behavior of instructions
- 3 Configuration
- 3.1 About configuration
- 3.2 Internal coprocessor instructions
- 3.3 Registers
- 3.3.1 ID Register
- 3.3.2 Control Register
- 3.3.3 Translation Table Base Register
- 3.3.4 Domain Access Control Register
- 3.3.5 Fault Status Register
- 3.3.6 Fault Address Register
- 3.3.7 Cache Operations Register
- 3.3.8 TLB Operations Register
- 3.3.9 Process Identifier Registers
- 3.3.10 Register 14, reserved
- 3.3.11 Test Register
- 4 Instruction and Data Cache
- 5 Write Buffer
- 6 The Bus Interface
- 7 Memory Management Unit
- 7.1 About the MMU
- 7.2 MMU program-accessible registers
- 7.3 Address translation
- 7.3.1 Translation Table Base Register
- 7.3.2 Level one fetch
- 7.3.3 Level one descriptor
- 7.3.4 Section descriptor
- 7.3.5 Coarse page table descriptor
- 7.3.6 Fine page table descriptor
- 7.3.7 Translating section references
- 7.3.8 Level two descriptor
- 7.3.9 Translating large page references
- 7.3.10 Translating small page references
- 7.3.11 Translating tiny page references
- 7.3.12 Subpages
- 7.4 MMU faults and CPU aborts
- 7.5 Fault address and fault status registers
- 7.6 Domain access control
- 7.7 Fault checking sequence
- 7.8 External aborts
- 7.9 Interaction of the MMU and cache
- 8 Coprocessor Interface
- 9 Debugging Your System
- 9.1 About debugging your system
- 9.2 Controlling debugging
- 9.3 Entry into debug state
- 9.4 Debug interface
- 9.5 ARM720T core clock domains
- 9.6 The EmbeddedICE-RT macrocell
- 9.7 Disabling EmbeddedICE-RT
- 9.8 EmbeddedICE-RT register map
- 9.9 Monitor mode debugging
- 9.10 The debug communications channel
- 9.11 Scan chains and the JTAG interface
- 9.12 The TAP controller
- 9.13 Public JTAG instructions
- 9.14 Test data registers
- 9.15 Scan timing
- 9.16 Examining the core and the system in debug state
- 9.17 Exit from debug state
- 9.18 The program counter during debug
- 9.19 Priorities and exceptions
- 9.20 Watchpoint unit registers
- 9.21 Programming breakpoints
- 9.22 Programming watchpoints
- 9.23 Abort status register
- 9.24 Debug control register
- 9.25 Debug status register
- 9.26 Coupling breakpoints and watchpoints
- 9.27 EmbeddedICE-RT timing
- 10 ETM Interface
- 11 Test Support
- 11.1 About the ARM720T test registers
- 11.2 Automatic Test Pattern Generation (ATPG)
- 11.3 Test State Register
- 11.4 Cache test registers and operations
- 11.5 MMU test registers and operations
- A.1 AMBA interface signals
- A.2 Coprocessor interface signals
- A.3 JTAG and test signals
- A.4 Debugger signals
- A.5 Embedded trace macrocell interface signals
- A.6 ATPG test signals
- A.7 Miscellaneous signals
- Appendix A Signal Descriptions
- Glossary
- Index