7 memory management unit, 1 about the mmu, About the mmu -1 – Epson ARM.POWERED ARM720T User Manual
Page 97: Chapter 7, Memory management unit
7: Memory Management Unit
ARM720T CORE CPU MANUAL
EPSON
7-1
7
Memory Management Unit
This chapter describes the
Memory Management Unit
(MMU). It contains the following
sections:
MMU program-accessible registers........................................................... 7-3
MMU faults and CPU aborts................................................................... 7-15
Fault address and fault status registers................................................. 7-16
Interaction of the MMU and cache.......................................................... 7-21
7.1
About the MMU
The ARM720T processor implements an enhanced ARM architecture v4 MMU to provide
translation and access permission checks for the instruction and data address ports of the
core. The MMU is controlled from a single set of two-level page tables stored in main memory,
that are enabled by the M bit in CP15 register 1, providing a single address translation and
protection scheme.
The MMU features are:
•
standard ARMv4 MMU mapping sizes, domains, and access protection scheme
•
mapping sizes are 1MB (sections), 64KB (large pages), 4KB (small pages), and 1KB
(tiny pages)
•
access permissions for sections
•
access permissions for large pages and small pages can be specified separately for
each quarter of the page (these quarters are called subpages)
•
16 domains implemented in hardware
•
64-entry TLB
•
hardware page table walks
•
round-robin replacement algorithm (also called cyclic)
•
invalidate whole TLB, using CP15 Register 8
•
invalidate TLB entry, selected by
Modified Virtual Address
(MVA), using CP15
Register 8.