Epson ARM.POWERED ARM720T - Manual (Page 161)

9: Debugging Your System
ARM720T CORE CPU MANUAL EPSON 9-29
When the ARM720T processor returns to debug state after a system speed access, bit 33 of
scan chain 1 is set HIGH. The state of bit 33 gives the debugger information about why the
core entered debug state the first time this scan chain is read.
9.17 Exit from debug state
Leaving debug state involves:
• restoring the ARM720T processor internal state
• causing the execution of a branch to the next instruction
• returning to normal operation.
After restoring the internal state, a branch instruction must be loaded into the pipeline. See
The program counter during debug on page 9-30 for details on calculating the branch.
Bit 33 of scan chain 1 forces the ARM720T processor to resynchronize back to HCLKEN, clock
enable. The penultimate instruction of the debug sequence is scanned in with bit 33 set HIGH.
The final instruction of the debug sequence is the branch, which is scanned in with bit 33 LOW.
The core is then clocked to load the branch instruction into the pipeline, and the RESTART
instruction is selected in the TAP controller.
When the state machine enters the RUN-TEST/IDLE state, the scan chain reverts back to
System mode. The ARM720T processor then resumes normal operation, fetching instructions
from memory. This delay, until the state machine is in the RUN-TEST/IDLE state, enables
conditions to be set up in other devices in a multiprocessor system without taking immediate
effect. When the state machine enters the RUN-TEST/IDLE state, all the processors resume
operation simultaneously.
DBGACK informs the rest of the system when the ARM720T processor is in debug state. This
information can be used to inhibit peripherals, such as watchdog timers, that have real-time
characteristics. DBGACK can also mask out memory accesses caused by the debugging
process.
For example, when the ARM720T processor enters debug state after a breakpoint, the
instruction pipeline contains the breakpointed instruction, and two other instructions that
have been prefetched. On entry to debug state the pipeline is flushed. On exit from debug state
the pipeline must therefore revert to its previous state.
Because of the debugging process, more memory accesses occur than are expected normally.
DBGACK can inhibit any system peripheral that might be sensitive to the number of memory
accesses. For example, a peripheral that counts the number of memory cycles must return the
same answer after a program has been run with and without debugging. Figure 9-11 shows
the behavior of the ARM720T processor on exit from the debug state.
Figure 9-11 Debug exit sequence
HCLK
DBGACK
Internal cycles N S S
Ab Ab+8 Ab+4
DATA[31:0]
HADDR[31:0]
HTRANS