Epson ARM.POWERED ARM720T - Manual (Page 222)

Index
Index-4 EPSON ARM DDI 0229B
SWI 2-13
System mode 2-4
System speed
instruction 9-28, 9-31
System state
determining 9-28
T
T bit (in CPSR) 2-8
TAP
controller 9-3, 9-10, 9-19
controller state
transitions 9-19
instruction 9-23
state 9-24
Test
registers 11-1
state register 11-3
Test Access Port, See TAP
Test data registers 9-22
Thumb instruction set 1-14
Thumb state 2-1
register organization 2-6
Tiny page references, translating
7-14
Transfer response
AHB 6-10
Transitions
TAP controller state 9-19
Translating page tables 7-5
Translation faults 7-15, 7-20
Translation Table Base Register
(TTB) 7-4
U
Undefined instruction
handling 8-10
trap 8-10
Undefined instruction trap 2-13
Undefined mode 2-4
UPDATE-DR 9-20
UPDATE-IR 9-23
User mode 2-4
W
Watchpoint 9-5, 9-6, 9-10, 9-24,
9-30, 9-43
aborted 9-31
coupling 9-43
EmbeddedICE-RT 9-36
externally generated 9-5
programming 9-38
register 9-33, 9-37
registers 9-33
programming and reading
9-33
unit 9-38
with exception 9-32
Watchpoint 0 9-44
Watchpointed
access 9-31, 9-33
memory access 9-31
Watchpoints
programming 9-38
WRITE 9-35
Write buffer
bufferable bit 5-1
operation 5-2
bufferable write 5-2
read-lock-write 5-2
unbufferable write 5-2
Write data bus
AHB 6-10