Epson ARM.POWERED ARM720T - Manual (Page 174)

9: Debugging Your System
9-42 EPSON ARM720T CORE CPU MANUAL
The structure of the debug control and status registers is shown in Figure 9-17.
Figure 9-17 Debug control and status register structure
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
Bit 2
Bit 1
Debug
control
register
Debug
status
register
TBIT
(from core)
TRANS[1]
(from core)
+
+
+
+
DBGACKI
(from core)
Interrupt mask enable
(to core)
DBGRQ
(from ARM720T input)
DBGACKI
(from core)
DBGACK
(to ARM720T processor
output)
DBGRQI
(to core)