Epson ARM.POWERED ARM720T - Manual (Page 193)

11: Test Support
ARM720T CORE CPU MANUAL EPSON 11-9
The CP15 register c15 operations that operate on the CAM, RAM1, and RAM2 are shown in
Table 11-5.
Note:
For the CAM match, RAM1 read operation a TLB miss will not cause a page walk.
These register c15 operations are all issued as MCR, which means that the read and match
operations have to be latched into register CP15.M in CP15. This is a 32-bit register that is
read with the following CP15 MRC instruction:
Read from register CP15.M
Table 11-6 summarizes register c2, c3, c5, c6, c8, c10, and c15 operations.
Table 11-5 CAM, RAM1, and RAM2 register c15 operations
Function Rd Data
CAM read to C15.M SBZ Tag, Size, V, P
CAM write Tag, Size, V, P
RAM1 read to C15.M SBZ Protection
RAM1 write Protection
RAM2 read to C15.M SBZ PA Tag, Size
RAM2 write PA Tag, Size PA Tag, Size
CAM match RAM1 read to C15.M MVA Fault, Miss, Protection
Table 11-6 Register c2, c3, c5, c6, c8, c10, and c15 operations
Function Rd Instruction(s)
Read Translation Table Base Register TTB MRC p15, 0, , c2, c0, 0
Write Translation Table Base Register TTB MCR p15, 0, , c2, c0, 0
Read domain [15:0] access control DAC MRC p15, 0, , c3, c0, 0
Write domain [15:0] access control DAC MCR p15, 0, , c3, c0, 0
Read FSR FSR MRC p15, 0, , c5, c0, 0
Write FSR FSR MCR p15, 0, , c5, c0, 0
Read FAR FAR MRC p15, 0, , c6, c0, 0
Write FAR FAR MCR p15, 0, , c6, c0, 0
Invalidate TLB SBZ MCR p15, 0, , c8, c5, 0
MCR p15, 0, , c8, c6, 0
MCR p15, 0, , c8, c7, 0
Invalidate TLB single entry (using MVA) MVA format MCR p15, 0, , c8, c5, 1
MCR p15, 0, , c8, c6, 1
MCR p15, 0, , c8, c7, 1
Read TLB lockdown TLB lockdown MRC p15, 0, , c10, c0, 0
Write TLB lockdown TLB lockdown MCR p15, 0, , c10, c0, 0
CAM read to C15.M SBZ MCR p15, 4, , c15, c7, 4
CAM write Tag, Size, V, P MCR p15, 4, , c15, c7, 0
RAM1 read to C15.M SBZ MCR p15, 4, , c15, c11, 4