DBGRQ must be deasserted on the same clock that DBGACK is asserted.
When the DBGRQ pin has been asserted, the core normally enters debug state at the end of

the current instruction. However, when the current instruction is a busy-waiting access to a

coprocessor, the instruction terminates, and the ARM720T core enters debug state

immediately. This is similar to the action of nIRQ and nFIQ.

9.3.4

Action of the ARM720T processor in debug state

When the ARM720T processor enters debug state, the core forces HTRANS[1:0] to indicate

internal cycles. This action enables the rest of the memory system to ignore the ARM720T core

and to function as normal. Because the rest of the system continues to operate, the ARM720T

core is forced to ignore aborts and interrupts.

Caution:

Do not reset the core while debugging, otherwise the debugger loses track of the

core.

Note:

The system must not change the ETMBIGEND signal during debug. From the

point of view of the programmer, if ETMBIGEND changes, the ARM720T processor

changes, with the debugger unaware that the core has reset. You must also ensure

that HRESETn is held stable during debug. When the system applies reset to the

ARM720T processor (that is, HRESETn is driven LOW), the ARM720T processor

state changes with the debugger unaware that the core has reset.