Epson ARM.POWERED ARM720T - Manual (Page 32)

1: Introduction
1-12 EPSON ARM720T CORE CPU MANUAL
Addressing mode 4 (store), , is shown in Table 1-7.
Addressing mode 5 (coprocessor data transfer), , is shown in Table 1-8.
Operand 2, , is shown in Table 1-9.
Fields, {field}, are shown in Table 1-10.
Table 1-7 Addressing mode 4 (store)
Addressing mode Stack type
IA Increment after EA Empty ascending
IB Increment before FA Full ascending
DA Decrement after ED Empty descending
DB Decrement before FD Full descending
Table 1-8 Addressing mode 5
Operation Assembler
Immediate offset [, #+/-<8bit_Offset*4>]
Pre-indexed [, #+/-<8bit_Offset*4>]!
Post-indexed [], #+/-<8bit_Offset*4>
Table 1-9 Operand 2
Operation Assembler
Immediate value #<32bit_Imm>
Logical shift left LSL #<5bit_Imm>
Logical shift right LSR #<5bit_Imm>
Arithmetic shift right ASR #<5bit_Imm>
Rotate right ROR #<5bit_Imm>
Register
Logical shift left LSL
Logical shift right LSR
Arithmetic shift right ASR
Rotate right ROR
Rotate right extended RRX
Table 1-10 Fields
Suffix Sets
_c Control field mask bit (bit 3)
_f Flags field mask bit (bit 0)
_s Status field mask bit (bit 1)
_x Extension field mask bit (bit 2)