Epson ARM.POWERED ARM720T - Manual (Page 176)

9: Debugging Your System
9-44 EPSON ARM720T CORE CPU MANUAL
9.26.2 DBGRNG signal
The DBGRNG signal is derived as follows:
DBGRNG = ((({Av[31:0],Cv[4:0]} XNOR {A[31:0],C[4:0]}) OR {Am[31:0],Cm[4:0]}) ==
0xFFFFFFFFF) AND
((({Dv[31:0],Cv[7:5]} XNOR {D[31:0],C[7:5]}) OR
Dm[31:0],Cm[7:5]}) == 0x7FFFFFFFF)
The DBGRNG output of watchpoint register 1 provides the RANGE input to watchpoint
register 0. This RANGE input enables you to couple two breakpoints together to form range
breakpoints.
Note:
Selectable ranges are restricted to being powers of 2.
For example, if a breakpoint is to occur when the address is in the first 256 bytes of memory,
but not in the first 32 bytes, program the watchpoint registers as follows:
For Watchpoint 1:
1 Program Watchpoint 1 with an address value of 0x00000000 and an address mask
of 0x0000001F.
2 Clear the ENABLE bit.
3 Program all other Watchpoint 1 registers as normal for a breakpoint.
An address within the first 32 bytes causes the RANGE output to go HIGH but does
not trigger the breakpoint.
For Watchpoint 0:
1 Program Watchpoint 0 with an address value of 0x00000000, and an address mask
of 0x000000FF.
2 Set the ENABLE bit.
3 Program the RANGE bit to match a 0.
4 Program all other Watchpoint 0 registers as normal for a breakpoint.
If Watchpoint 0 matches but Watchpoint 1 does not (that is, the RANGE input to Watchpoint
0 is 0), the breakpoint is triggered.
9.27 EmbeddedICE-RT timing
EmbeddedICE-RT samples the DBGEXT[1] and DBGEXT[0] inputs on the rising edge of
HCLK.