Epson ARM.POWERED ARM720T - Manual (Page 152)

9: Debugging Your System
9-20 EPSON ARM720T CORE CPU MANUAL
9.13 Public JTAG instructions
Table 9-4 shows the public JTAG instructions.
In the following descriptions, the ARM720T processor samples DBGTDI and DBGTMS on the
rising edge of HCLK with DBGTCKEN HIGH. The TAP controller states are shown in
Figure 9-8 on page 9-19.
9.13.1 SCAN_N (b0010)
The SCAN_N instruction connects the scan path select register between DBGTDI and
DBGTDO:
• In the CAPTURE-DR state, the fixed value b1000 is loaded into the register.
• In the SHIFT-DR state, the ID number of the desired scan path is shifted into the
scan path select register.
• In the UPDATE-DR state, the scan register of the selected scan chain is connected
between DBGTDI and DBGTDO, and remains connected until a subsequent
SCAN_N instruction is issued.
• On reset, scan chain 0 is selected by default.
The scan path select register is 4 bits long in this implementation, although no finite length is
specified.
9.13.2 INTEST (b1100)
The INTEST instruction places the selected scan chain in test mode:
• The INTEST instruction connects the selected scan chain between DBGTDI and
DBGTDO.
• When the INTEST instruction is loaded into the instruction register, all the scan
cells are placed in their test mode of operation.
• In the CAPTURE-DR state, the value of the data applied from the core logic to the
output scan cells, and the value of the data applied from the system logic to the
input scan cells is captured.
• In the SHIFT-DR state, the previously-captured test data is shifted out of the scan
chain through the DBGTDO pin, while new test data is shifted in through the
DBGTDI pin.
Single-step operation of the core is possible using the INTEST instruction.
Table 9-4 Public instructions
Instruction Binary code
SCAN_N b0010
INTEST b1100
IDCODE b1110
BYPASS b1111
RESTART b0100