Epson ARM.POWERED ARM720T - Manual (Page 31)

1: Introduction
ARM720T CORE CPU MANUAL EPSON 1-11
Addressing mode 2 (privileged), , is shown in Table 1-4.
Addressing mode 3 (signed byte, and halfword data transfer), , is shown in
Table 1-5.
Addressing mode 4 (load), , is shown in Table 1-6.
Table 1-4 Addressing mode 2 (privileged)
Operation Assembler
Immediate offset [, #+/-<12bit_Offset>]
Register offset [, +/-]
Scaled register offset [, +/-, LSL #<5bit_shift_imm>]
[, +/-, LSR #<5bit_shift_imm>]
[, +/-, ASR #<5bit_shift_imm>]
[, +/-, ROR #<5bit_shift_imm>]
[, +/-, RRX]
Post-indexed immediate offset [], #+/-<12bit_Offset>
Post-indexed register offset [], +/-
Post-indexed scaled register offset [], +/-, LSL #<5bit_shift_imm>
[], +/-, LSR #<5bit_shift_imm>
[], +/-, ASR #<5bit_shift_imm>
[], +/-, ROR #<5bit_shift_imm>
[, +/-, RRX]
Table 1-5 Addressing mode 3
Operation Assembler
Immediate offset [, #+/-<8bit_Offset>]
Pre-indexed [, #+/-<8bit_Offset>]!
Post-indexed [], #+/-<8bit_Offset>
Register [, +/-]
Pre-indexed [, +/-]!
Post-indexed [], +/-
Table 1-6 Addressing mode 4 (load)
Addressing mode Stack type
IA Increment after FD Full descending
IB Increment before ED Empty descending
DA Decrement after FA Full ascending
DB Decrement before EA Empty ascending