Epson ARM.POWERED ARM720T - Manual (Page 81)

6: The Bus Interface
ARM720T CORE CPU MANUAL EPSON 6-1
6 The Bus Interface
This chapter describes the signals on the bus interface of the ARM720T processor. It contains
the following sections:
6.1 About the bus interface.............................................................................. 6-1
6.2 Bus interface signals.................................................................................. 6-3
6.3 Transfer types............................................................................................. 6-5
6.4 Address and control signals....................................................................... 6-7
6.5 Slave transfer response signals................................................................. 6-9
6.6 Data buses ................................................................................................ 6-10
6.7 Arbitration ................................................................................................ 6-12
6.8 Bus clocking.............................................................................................. 6-13
6.9 Reset.......................................................................................................... 6-13
6.1 About the bus interface
The ARM720T processor is an Advanced High-performance Bus (AHB) bus master. To ensure
reuse of your design with other ARM processors, including different revisions, it is strongly
recommended that you use fully AMBA-compliant peripherals and interfaces early in your
design cycle. The AHB timings described in this chapter are examples only, and do not provide
a complete list of all possible accesses.
For more details on AMBA interface and integration see the
AMBA specification .
6.1.1 Summary of the AHB transfer mechanism
An AHB transfer comprises the following:
Address phase This lasts only a single cycle. The address cannot be extended, so
all slaves must sample the address during the address phase.
Data phase
This phase can be extended using the HREADY signal. When LOW,
HREADY causes wait states to be inserted into the transfer and enables extra
time for a slave to provide or sample data.
A write data bus is used to move data from the master to a slave.
A read data bus is used to move data from a slave to the master.