Altera Low Latency Ethernet 10G MAC - Manual (Page 96)

Signal Condition Direction Width Description
xgmii_tx[]
Use legacy Ethernet
10G MAC XGMII
interface enabled.
Out 72
8-lane SDR XGMII transmit data and
control bus. Each lane contains 8 data
plus 1 control bits. The signal mapping
is compatible with the 64b MAC.
• Lane 0 data:
xgmii_tx[7:0]
• Lane 0 control:
xgmii_tx[8]
• Lane 1 data:
xgmii_tx[16:9]
• Lane 1 control:
xgmii_tx[17]
• Lane 2 data:
xgmii_tx[25:18]
• Lane 2 control:
xgmii_tx[26]
• Lane 3 data:
xgmii_tx[34:27]
• Lane 3 control:
xgmii_tx[35]
• Lane 4 data:
xgmii_tx[43:36]
• Lane 4 control:
xgmii_tx[44]
• Lane 5 data:
xgmii_tx[52:45]
• Lane 5 control:
xgmii_tx[53]
• Lane 6 data:
xgmii_tx[61:54]
• Lane 6 control:
xgmii_tx[62]
• Lane 7 data:
xgmii_tx[70:63]
• Lane 7 control:
xgmii_tx[71]
link_fault_
status_xgmii_
tx_data[]
— In 2 This signal is present in the MAC TX
only variation. Connect this signal to the
corresponding RX client logic to handle
the local and remote faults. The
following values indicate the link fault
status:
• 0x0: No link fault
• 0x1: Local fault
• 0x2: Remote fault
5-14 XGMII TX Signals
UG-01144
2014.12.15
Altera Corporation Interface Signals for LL Ethernet 10G MAC
Send Feedback