Altera Low Latency Ethernet 10G MAC - Manual (Page 8)

Configuration Arria V GX/GT/
GZ
Arria 10 Stratix V
10G MAC with Arria 10 Transceiver Native PHY
presets:
• 10GBASE-R
• 10GBASE-R Low Latency
• 10GBASE-R Register Mode
• 10GBASE-R w/KR-FEC
No Yes No
10M/100M/1G/10G MAC Arria V GZ Yes Yes
10M/100M/1G/10G MAC with IEEE 1588v2 Arria V GZ Yes Yes
10M/100M/1G/10G MAC with Backplane
Ethernet 10GBASE-KR PHY
Arria V GZ Yes Yes
10M/100M/1G/10G MAC with 1G/10GbE PHY
MegaCore function and IEEE 1588v2
Arria V GZ Yes Yes
Definition: Device Support Level
Altera IP cores provide the following support for Altera device families:
• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. This IP core can be used in production designs with caution.
• Final support—Altera verifies with IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. This IP core is ready to be used in
production designs.
Performance and Resource Utilization
Resource Utilization
The following resource estimation is obtained by compiling the LL 10GbE MAC with the Quartus II
software targeting a commercial Stratix V. These estimates are based on the number of ALMs needed
minus the recoverable and unavailable ALMs due to the virtual I/Os (in Quartus II Fitter terms). The
estimates also apply to other supported devices.
Table 1-4: Resource Utilization for LL Ethernet 10G MAC
MAC Settings
ALMs ALUTs
Logic
Registers
Memory Block
Operating
Mode
Enabled Options
10G None. 1,600 2,400 2,800 0
10G Memory-based statistics counters. 2,100 3,200 3,900 4 (M20K)
10M/
100M/
1G/10G
Memory-based statistics counters. 2,600 3,900 5,000 4 (M20K)
1-4 Definition: Device Support Level
UG-01144
2014.12.15
Altera Corporation About LL Ethernet 10G MAC
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