Altera Low Latency Ethernet 10G MAC - Manual (Page 77)

Table 4-18: ECC Registers
Word Offset Register Name Description Access HW Reset
Value
0x0240
ecc_status • Bit 0—a value of '1' indicates that an ECC
error was detected and corrected. Once
set, the client must write a '1' to this bit to
clear it.
• Bit 1—a value of '1' indicates that an ECC
error was detected but not corrected.
Once set, the client must write a '1' to this
bit to clear it.
• Bits 31:2—reserved.
RW1C 0x0
0x0241
ecc_enable • Bit 0—specifies how detected and
corrected ECC errors are reported.
0: Reported by the
ecc_status[0]
register bit only.
1: Reported by the
ecc_status[0]
register bit and the
ecc_err_det_corr
signal.
• Bit 1—specifies how detected and
uncorrected ECC errors are reported.
0: Reported by the
ecc_status[0]
register bit only.
1: Reported by the
ecc_status[0]
register bit and the
ecc_err_det_uncorr
signal.
• Bits 31:2—reserved.
RW 0x0
Statistics Registers
Statistics counters with prefix
tx_
collect statistics on the TX datapath; prefix
rx_
collect statistics on the
RX datapath. The counters collect statistics for the following frames:
• Good frame—error-free frames with a valid frame length.
• Error frame—frames that contain errors or with an invalid frame length.
• Invalid frame—frames that are not supported by the MAC IP core. It may or may not contain error
within the frame or have an invalid frame length. The MAC drops invalid frames.
The statistics counters are 36 bits wide and counters occupy two offsets. The user application must first
read the lower 32 bits followed by the upper 4 bits.
• The lower 32 bits of the counter occupy the first offset.
• The upper 4 bits of the counter occupy bits 3:0 at the second offset.
• Bits 31:5 at the second offset are reserved.
UG-01144
2014.12.15
Statistics Registers 4-25
Configuration Registers for LL Ethernet 10G MAC Altera Corporation
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