Altera Low Latency Ethernet 10G MAC User Manual
Page 46
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Figure 3-20: Fault Signaling
Remote Fault (0x9c000002)
Idle (07070707)
Remote Fault (0x9c000002)
Client
Interface
MAC
Tx
RS Tx
MAC
Rx
RS Rx
2
link_fault_status_xgmii_rx_data
XAUI /
10GBASE-R
PHY
External
PHY
Remote
Partner
XAUI /
10GBASE-R
Network
Interface
Local Fault (0x9c000001)
XGMII
Figure 3-21: XGMII TX interface Transmitting Remote Fault Signal
The following figure shows the timing for the XGMII TX interface transmitting the remote fault signal
(0x9c000002).
tx_clk_clk
xgmii_tx_control[3]
xgmii_tx_data[31:24]
xgmii_tx_control[2]
xgmii_tx_data[23:16]
xgmii_tx_control[1]
xgmii_tx_data[15:8]
xgmii_tx_control[0]
xgmii_tx_data[7:0]
02
00
00
9C
When you instantiate the MAC RX only variation, connect the
link_fault_status_xgmii_rx_data
signal to the corresponding RX client logic to handle the link fault. Similarly, when you instantiate the
MAC TX only variation, connect the
link_fault_status_xgmii_tx_data
signal to the corresponding
TX client logic.
3-24
XGMII Error Handling (Link Fault)
UG-01144
2014.12.15
Altera Corporation
Functional Description of LL Ethernet 10G MAC
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)