Dual clock fifo – Altera Low Latency Ethernet 10G MAC User Manual
Page 22
The timing constraint file uses the
set_net_delay
to constraint the fitter placement and
set_max_skew
to
perform timing check on the paths. For a project with very high device utilization, Altera recommends
that you implement addition steps like floor planning or LogicLock to aid the place-and-route process.
The additional steps can give a more consistent timing closure along these paths instead of only relying on
the
set_net_delay
.
A caveat of using
set_max_skew
is that it does not analyze whether the insertion delay of the path in
concern exceeds a limit. In other words, a path could meet skew requirement but have longer than
expected insertion delay. If this is not checked, it may cause functional failure in certain latency-sensitive
paths. Therefore, a custom script (
alt_em10g32_clock_crosser_timing_info.tcl
) is available for you to check
that the round-trip clock crosser delay is within expectation. To use this script, manually add it to the user
flow and run it. To ensure that the IP core operates correctly, the results must be positive (no error).
Dual Clock FIFO
The bit skew of the dual clock FIFO gray-coded pointers must be within one 312.5 MHz clock period.
The timing constraint file uses the
set_net_delay
to constraint the fitter placement and
set_max_skew
to
perform timing check on the paths. For a project with very high device utilization, Altera recommends
that you implement addition steps like floor planning or LogicLock to aid the place-and-route process.
The additional steps can give a more consistent timing closure along these paths instead of only relying on
the
set_net_delay
.
UG-01144
2014.12.15
Dual Clock FIFO
2-13
Getting Started with LL Ethernet 10G MAC
Altera Corporation