Altera Low Latency Ethernet 10G MAC - Manual (Page 72)

Word
Offset
Register Name Description Access HW Reset
Value
0x10A
tx_fns_adjustment_mult_
speed
Static timing adjustment in fractional
nanoseconds on the TX datapath for 10M/
100M/1G operations.
• Bits 15:0—adjustment period in
fractional nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x10C
tx_ns_adjustment_mult_
speed
Static timing adjustment in nanoseconds
on the TX datapath for 10M/100M/1G
operations.
• Bits 15:0—adjustment period in
nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
Calculating TX Timing Adjustments
You can derive the required timing adjustments in ns and fns from the hardware PMA delay.
Table 4-11: Hardware PMA Delay
Type Device PMA Mode
(bit)
Latency (9) MAC Configurations
Digital
Arria V GZ and
Stratix V
40 123 UI 10GbE or 10G of 10M-10GbE
32 99 UI 10GbE
10 53 UI 1G/100M/10M of 10M-10GbE
Analog (10) Arria V GZ and
Stratix V
— –1.1 ns All
The example below shows the required calculation for a 10M – 10GbE design targeting a Stratix V device.
Table 4-12: Example: Calculating Timing Adjustments for 10M – 10GbE Design in Stratix V Device
Step Description 10G 10M, 100M or 1G
1 Identify the digital
latency for the device.
For Stratix V using the PMA mode of
40 bits, the digital latency is 123 UI.
For Stratix V using the PMA mode
of 10 bits, the digital latency is 53
UI.
(9) For 10G: 1 UI = 97 ps; for 10M/100M/1G: 1 UI = 800 ps
(10) Valid for the HSSI clock routing using periphery clock. Other clocking scheme might result in deviation of a
few ns.
4-20 Calculating TX Timing Adjustments
UG-01144
2014.12.15
Altera Corporation Configuration Registers for LL Ethernet 10G MAC
Send Feedback