Altera Low Latency Ethernet 10G MAC - Manual (Page 42)

PFC Frame Reception
When the MAC RX receives a PFC frame from the remote partner, it asserts the
avalon_st_rx_pfc_pause_data[n]
signal if Pause Quanta n is valid (Pause Quanta Enable [n] = 1) and
greater than 0. The client suspends transmission from the TX priority queue n for the period specified by
Pause Quanta n. If the MAC RX asserts the
avalon_st_rx_pfc_pause_data[n]
signal in the middle of a
client frame transmission for the TX priority queue n, the client finishes sending the current frame and
then suspends transmission for the queue.
When the MAC RX receives a PFC frame from the remote partner, it deasserts the
avalon_st_rx_pfc_pause_data[n]
signal if Pause Quanta n is valid (Pause Quanta Enable [n] = 1) and
equal to 0. The MAC RX also deasserts this signal when the timer expires. The client resumes transmis‐
sion for the suspended TX priority queue when the
avalon_st_rx_pfc_pause_data[n]
signal is
deasserted.
When the remote partner sends more than one pause quanta for the TX priority queue n, the MAC RX
sets the pause quanta n to the last pause quanta received from the remote partner.
PFC Frame Transmission
PFC frame generation is triggered through the
avalon_st_tx_pfc_gen_data
signal. Set the respective
bits to generate XOFF or XON requests for the priority queues.
For XOFF requests, you can configure the pause quanta for each priority queue using the
pfc_pause_quanta_n
registers. For an XOFF request for priority queue n, the MAC TX sets bit n in the
Pause Quanta Enable field to 1 and the Pause Quanta n field to the value of the
pfc_pause_quanta_n
register. You can also configure the gap between successive XOFF requests for a priority queue using the
pfc_holdoff_quanta_n
register.
For XON requests, the MAC TX sets the pause quanta to 0. You must generate a XOFF request before
generating a XON request.
Reset Requirements
The MAC IP core consists of the following reset domains:
• CSR reset—global reset,
• MAC TX reset, and
• MAC RX reset.
These resets are asynchronous events. When the MAC or any part of it goes into reset, the user applica‐
tion must manage possible asynchronous changes to the states of the MAC interface signals. The MAC
does not guarantee any reset sequence. Altera recommends the sequence shown in the following diagram
and table for CSR reset, and TX and RX datapaths reset respectively.
3-20 PFC Frame Reception
UG-01144
2014.12.15
Altera Corporation Functional Description of LL Ethernet 10G MAC
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