Altera Low Latency Ethernet 10G MAC - Manual (Page 17)

Figure 2-3: Simulation in Quartus II Design Flow
Post-fit timing
simulation netlist
Post-fit timing
simulation
(3)
Post-fit functional
simulation netlist
Post-fit functional
simulation
Analysis & Synthesis
Fitter
(place-and-route)
TimeQuest Timing Analyzer
Device Programmer
Quartus II
Design Flow
Gate-Level Simulation
Post-synthesis
functional
simulation
Post-synthesis functional
simulation netlist
(Optional) Post-fit
timing simulation
RTL Simulation
Design Entry
(HDL, Qsys, DSP Builder)
Altera Simulation
Models
EDA
Netlist
Writer
Note: Post-fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current
version of the Quartus II software. Altera IP supports a variety of simulation models, including
simulation-specific IP functional simulation models and encrypted RTL models, and plain text
RTL models. These are all cycle-accurate models. The models support fast functional simulation of
your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores,
only the plain text RTL model is generated, and you can simulate that model. Use the simulation
models only for simulation and not for synthesis or any other purposes. Using these models for
synthesis creates a nonfunctional design.
Related Information
Simulating Altera Designs
Upgrading Outdated IP Cores
Altera IP components are version-specific with the Quartus II software. The Quartus II software alerts
you when your IP core is outdated. Click Project > Upgrade IP Components to easily identify and
upgrade outdated IP cores.
To upgrade outdated IP cores appropriately, your restored project archive must retain the original
Quartus II-generated file structure. Failure to upgrade outdated IP cores can result in a mismatch between
the outdated IP core variation and the current supporting libraries.
2-8 Upgrading Outdated IP Cores
UG-01144
2014.12.15
Altera Corporation Getting Started with LL Ethernet 10G MAC
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