Altera Low Latency Ethernet 10G MAC - Manual (Page 16)

Extension Description
<variation name>.qip Contains Quartus II project information for your MegaCore function
variation.
<variation name>.bsf Quartus II symbol file for the MegaCore function variation. Use this file in
the Quartus II block diagram editor.
<variation name>.sip Contains IP core library mapping information required by the Quartus II
software.The Quartus II software generates a . sip file during generation of
some Altera IP cores. You must add any generated .sip file to your project
for use by NativeLink simulation and the Quartus II Archiver.
<variation name>.spd Contains a list of required simulation files for your MegaCore function.
Simulating Altera IP Cores in other EDA Tools
The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling
simulation model libraries, and running your simulation.
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
UG-01144
2014.12.15
Simulating Altera IP Cores in other EDA Tools 2-7
Getting Started with LL Ethernet 10G MAC Altera Corporation
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