Altera Low Latency Ethernet 10G MAC - Manual (Page 21)

Migration—Maintains 64-bit on Avalon-ST Interface
This migration path implements 32-bit to 64-bit adapters on the Avalon ST interface and XGMII, and
uses the same register offsets to maintain backward compatibility with the legacy 10-Gbps Ethernet
(10GbE) MAC IP Core.
1. Instantiate the LL Ethernet 10G MAC IP core in your design. To maintain compatibility on the
interfaces, turn on the Use legacy Ethernet 10G MAC XGMII Interface, Use legacy Ethernet 10G
MAC Avalon Memory-Mapped Interface, and Use legacy Ethernet 10G MAC Avalon Streaming
Interface options.
2. Ensure that
tx_312_5_clk
and
rx_312_5_clk
are connected to 312.5-MHz clock sources. Altera
recommends that you use the same clock source for these clock signals.
3. Add a 156.25-MHz clock source for
tx_156_25_clk
and
rx_156_25_clk
. This 156.25 MHz clock
source must be rise-to-rise synchronous to the 312.5 MHz clock source.
4. Ensure that
csr_clk
is within 125 MHz to 156.25 MHz. Otherwise, some statistic counters may not be
accurate.
Timing Constraints
Altera provides timing constraint files ( .sdc ) to ensure that the IP core meets the design timing
requirements in Altera devices. The files constraints the false paths and multi-cycle paths in the IP core.
The timing constraints files are specified in the .qip file and is automatically included in
the Quartus II project files.
The timing constraints files are in the IP directory. You can edit these files as necessary. They are for clock
crossing logic and grouped as below:
• Pseudo-static CSR fields
• Clock crosser
• Dual clock FIFO
Note: For the IP to work correctly, there must be no other timing constraints files cutting or overriding
the paths, for example,
set_false_path
,
set_clock_groups
, at the project level.
Pseudo-Static CSR Fields
Most of the configuration registers in the MAC IP core must not be programmed when the MAC is in
operation. As such, they are not synchronized to reduce resource usage. These registers are all in the
set_false_path
constraint.
Clock Crosser
Clock crossers perform multi-bit signals crossing from one clock domain to another.
The working principle of the clock crosser is to let the crossed-over data stabilize first before indicating
that the data is valid in the latched clock domain. Using such structure, the data bits must not skew for
more than one latched clock period. The timing constraint file applies a common timing check over all
the clock crossers irrespective of their latched clock domain. This is over-pessimistic for signals crossing
into the CSR clock, but there are no side-effects, like significant run-time impact and false violations,
during the internal testing. If your design runs into clock crosser timing violation paths within the IP and
the latched clock domain is
csr_clk
, you can dismiss the violation manually or by editing the .sdc file if
the violation is less than one
csr_clk
period.
2-12 Migration—Maintains 64-bit on Avalon-ST Interface
UG-01144
2014.12.15
Altera Corporation Getting Started with LL Ethernet 10G MAC
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