Altera Low Latency Ethernet 10G MAC - Manual (Page 53)

Configuration Registers for LL Ethernet 10G
MAC
4
2014.12.15
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The LL Ethernet 10G MAC IP core provides a total of 4Kb register space that is accessible via the Avalon-
MM interface. Each register is 32 bits wide. Access only registers that apply to the variation of the MAC IP
core you are using and enabled features. For example, if you are using the MAC RX only variation, avoid
accessing registers specific to the MAC TX only variation. Accessing reserved registers or specific registers
to variations that you are not using may produce non-deterministic behavior.
Register Map
Table 4-1: Register Map
Word Offset Purpose Variation
0x0000: 0x000F Reserved —
0x0010: 0x0011 Primary MAC Address MAC TX, MAC RX
0x0012: 0x001D Reserved —
0x001F MAC Reset Control Register
0x0020: 0x003F TX Configuration and Status Registers MAC TX
0x0040: 0x005F TX Flow Control Registers MAC TX
0x0060: 0x006F Reserved —
0x0070 TX Unidirectional Control Register MAC TX
0x0071: 0x009F Reserved —
0x00A0: 0x00FF RX Configuration and Status Registers MAC RX
0x0100: 0x010C TX Timestamp Registers MAC TX
0x0120: 0x012C RX Timestamp Registers MAC RX
0x0140: 0x023F Statistics Registers MAC TX, MAC RX
0x0240: 0x0241 ECC Registers MAC TX, MAC RX
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